h-index:   37.     i10-index:   93.     g-index:   56.

Google Scholar Citations (J. Ramanujam)

Recent Publications (most in pdf)

Full List of Publications (some pdf included)

Publications (from Google Scholar)

Recent Articles (from Google Scholar)

Publications (from DBLP)

Publications (from the new DBLP)

Selected Recent Publications

• T. Henretty, R. Veras, F. Franchetti, L.N. Pouchet, J. Ramanujam and P. Sadayappan, “A Stencil Compiler for Short-Vector SIMD Architectures,” in Proc. 27th ACM International Conference on Supercomputing, Eugene, OR, June 2013.
• A. Cohen, T. Grosser, P. Kelly, J. Ramanujam, P. Sadayappan, and S. Verdoolaege, “Tiling for GPUs: Automatic Parallelization Using Trapezoidal Tiles to Reconcile Parallelism and Locality, Avoiding Divergence and Load Imbalance,” in Proc. 6th Workshop on General Purpose Processing Using GPUs (GPGPU-6), Houston, TX, held with ASPLOS-13, March 2013.
• Z. Yun, Z. Lei, G. Allen, D. Katz, and J. Ramanujam, “DA-TC: A Novel Application Execution Model in Multi-Cluster Systems, ” in Cluster Computing, 2013 (to appear).
• M. Ravishankar, J. Eisenlohr, L.-N. Pouchet, J. Ramanujam, A. Rountev and P. Sadayappan, “Code Generation for Parallel Execution of a Class of Irregular Loops on Distributed Memory Systems,” in Proc. ACM/IEEE Conference on High Performance Computing SC12, Salt Lake City, UT, November 2012.
• J. Shirako, K. Sharma, N. Fauzia, L.-N. Pouchet, J. Ramanujam, P. Sadayappan and V. Sarkar, "Analytical Bounds for Optimal Tile Size Selection," in CC 2012 - International Conference on Compiler Construction, (M. O'Boyle Ed.), Lecture Notes in Computer Science, Springer-Verlag, 2012.
• K.-M. Tam, H. Fotso, S.-X. Yang, T.-W. Lee, J. Moreno, J. Ramanujam and M. Jarrell, "Solving the Parquet Equations for the Hubbard Model beyond Weak Coupling," arXiv:1108.4926 to appear in Physical Review E, 2013.
• H. Salamy and J. Ramanujam, "An Effective Solution to Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012.
  
• H. Salamy and J. Ramanujam, "An ILP Solution to Address Code Generation for Embedded Applications on Digital Signal Processors," in ACM Transactions on Design Automation of Electronic Systems, 2012.
• H. Salamy and J. Ramanujam, "Storage Optimization through Offset Assignment with Variable Coalescing," in ACM Transactions on Embedded Computing Systems, 2012.
  
• H. Salamy and J. Ramanujam, "Code Size Reduction for Array Intensive Applications on Digital Signal Processors," in Journal of Circuits, Systems, and Computers, 2012.
  
• Q. Lu, X. Gao, S. Krishnamoorthy, G. Baumgartner, J. Ramanujam and P. Sadayappan, "Empirical Performance Model-Driven Data Layout Optimization and Library Call Selection for Tensor Contraction Expressions," in Journal of Parallel and Distributed Computing, 72(3):338-352, March 2012.
  
• S. Tavarageri, L.-N. Pouchet, J. Ramanujam, A. Rountev and P. Sadayappan, "Dynamic Selection of Tile Sizes," in 18th Annual International Conference on High Performance Computing (HiPC 2011), Bangalore, India, December 2011.
  
• T. Henretty, K. Stock, L.-N. Pouchet, F. Franchetti, J. Ramanujam and P. Sadayappan, "Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures," in International Conference on Compiler Construction (CC'2011), Saarbrucken, Germany, March 2011.
  
• L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam, P. Sadayappan and N. Vasilache, "Loop Transformations: Convexity, Pruning and Optimization," in Proc. Symposium on Principles of Programming Languages (POPL 11), Austin, TX, January 2011.
• L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam and P. Sadayappan, "Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework," in Proc. ACM/IEEE Conference on High Performance Computing SC10, New Orleans, LA, November 2010.
  
• M. Baskaran, A. Hartono, S. Tavarageri, T. Henretty, J. Ramanujam, and P. Sadayappan, "Parameterized Tiling Revisited," International Symposium on Code Generation and Optimization (CGO), Toronto, Canada, April 2010.
  
• M. Baskaran, J. Ramanujam, and P. Sadayappan, "Automatic C-to-CUDA Code Generation for Affine Programs," International Conference on Compiler Construction (CC), Paphos, Cyprus, March 2010.
  
• Q. Lu, C. Alias, U. Bondhugula, T. Henretty, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, Y. Chen, H. Lin, T. Ngai, "Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors," Proc. Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, September 2009.
  
• A. Hartono, M. Baskaran, C. Bastoul, A. Cohen, S. Krishnamoorthy, B. Norris, J. Ramanujam, and P. Sadayappan, "Parametric multi-level tiling of imperfectly nested loops," ACM International Conference on Supercomputing (ICS), New York, NY, June 2009.
  
• M. Baskaran, N. Vydhyanathan, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "Compiler-Assisted Dynamic Scheduling for Effective Parallelization of Loop Nests on Multicore Processors," in Proc. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, NC, February 2009.
  
• A. Hartono, Q. Lu, T. Henretty, S. Krishnamoorthy, H. Zhang, G. Baumgartner, D. E. Bernholdt, M. Nooijen, R. Pitzer, J. Ramanujam, and P. Sadayappan, "Performance Optimization of Tensor Contraction Expressions for Many-Body Methods in Quantum Chemistry," The Journal of Physical Chemistry A, Vol. 113 (45), pp. 12715-12723, 2009.
  
• Hassan Salamy and J. Ramanujam, "A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip," in Proc. 4th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC 2009), Paphos, Cyprus, January 2009.
  
• M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "A compiler framework for optimization of affine loop nests for GPGPUs," ACM International Conference on Supercomputing (ICS), June 2008.
  
• U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, "PLUTO: A Practical and Fully Automatic Polyhedral Program Optimization System," Proc. ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation (PLDI 08), Tucson, AZ, June 2008.
  
• U. Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan, "Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model," in Proc. CC 2008 - International Conference on Compiler Construction, March-April 2008.
  
• M. Baskaran, U. Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev and P. Sadayappan, "Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories," in Proc. 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (PPoPP 2008), Salt Lake City, UT, February 2008.
  
• H. Salamy and J. Ramanujam, "Optimal Address Register Allocation for Arrays in DSP Applications," in Proc. 6th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2008), pp. 67–72, Atlanta, GA, October 2008.
  
•  H. Salamy and J. Ramanujam, "Storage Optimization through Code Size Reduction for Digital Signal Processors," in Proc. 6th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2008), pp. 107–112, Atlanta, GA, October 2008.
• J. Hong and J. Ramanujam, "Scheduling DAGs for Fixed-point DSP Processors by Using Worm Partitions," in Proc. 2008 International Conference on Embedded Systems and Software (ICESS-08), pp. 567–574, Chengdu, China, July 2008.
  
• S. Krishnamoorthy, M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev and P. Sadayappan, "Effective Automatic Parallelization of Stencil Computations," in Proc. ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation (PLDI 07), San Diego, CA, June 2007.
  
• U. Bondhugula, J. Ramanujam, and P. Sadayappan, "Automatic Mapping of Nested Loops to FPGAs," in Proc. ACM SIGPLAN 2007 Symposium on Principles and Practice of Parallel Programming (PPoPP 07), San Jose, CA, March 2007.
  
• J. Ramanujam, J. Hong, M. Kandemir, A. Narayan, and A. Agarwal, "Estimating and Reducing the Memory Requirements of Signal Processing Codes for Embedded Processor Systems," IEEE Transactions on Signal Processing, vol. 54, no. 1, pp. 286--294, January 2006.
  
• G. Baumgartner, A. Auer, D. Bernholdt, A. Bibireata, V. Choppella, D. Cociorva, X. Gao, R. Harrison, S. Hirata, S. Krishnamoorthy, S. Krishnan, C. Lam, Q. Lu, M. Nooijen, R. Pitzer, J. Ramanujam, P. Sadayappan, and A. Sibiryakov, "Synthesis of High-Performance Parallel Programs for a Class of ab initio Quantum Chemistry Models," Proceedings of the IEEE, vol. 93, no. 2, pp. 276-292, February 2005.
  
• X. Gao, S. Sahoo, Q. Lu, G. Baumgartner, C. Lam, J. Ramanujam, and P. Sadayappan, "Performance Modeling and Optimization of Parallel Out-of-Core Tensor Contractions," in Proc. ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming, Chicago, IL, June 2005. 
  
• S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C. Lam, J. Ramanujam, P. Sadayappan, and V. Choppella, "Efficient Synthesis of Out-of-Core Algorithms Using a Nonlinear Optimization Solver," Journal of Parallel and Distributed Computing, vol. 66, no. 5, pp. 659-673, May 2006. An ealier version appears as: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C.-C. Lam, J. Ramanujam, and P. Sadayappan, "Efficient Synthesis of Out-of-core Algorithms Using a Nonlinear Optimization Solver," In Proceedings of the 18th International Parallel and Distributed Processing Symposium (2004 IPDPS Conference), April 2004. (Best Paper Award)  
  

 

Fall 2013: EE 7700: Program Optimization Using Polyhedral Models

Recent Courses

Spring 2013: EE 7785: Parallelizing Compilers	Fall 2012: EE 4702: High-Level Synthesis and Embedded Systems
Spring 2012: EE 4702: Software Optimizations	Fall 2011: EE 7700: Performance Optimization of Applications on GPUs (PDF)
Spring 2011: EE 7780: Software Design Principles	Fall 2010: EE 7785: Compiler Optimizations
Spring 2010: EE 4702: High-Level Synthesis	Fall 2009: EE 7000: Software Optimizations for Multicore
Spring 2009: EE 4760: Introduction to Compiler Optimizations	Fall 2008: EE 7785: Compiler Optimizations
Spring 2008: EE 4702: High-Level Synthesis & Embedded Systems	Fall 2007: EE 7785: Compiler Optimizations
Spring 2007: EE 4760: Introduction to Compiler Optimizations	Fall 2006: EE 7000: Embedded Systems
Spring 2006: EE 7000: High-Level Synthesis	Fall 2005: EE 7785: Compiler Optimizations
Spring 2005: EE 4760: Introduction to Compiler Optimizations	Fall 2004: EE 7700: Architectures & Algorithms for Digital Signal Processing (DSP)
Spring 2004: EE 7700: Energy Aware Computing Systems	Fall 2003: EE 4702: High Level Synthesis Fall 2003: EE 7700-1: Compiler Optimizations
Spring 2003: EE 7700: Embedded Systems

 

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