Teaching - Fall 2012:
EE
4702: High-Level Synthesis and Embedded Systems
J. (Ram) Ramanujam
| 102 Electrical Engineering Building | ECE Office: | +1 225-578-5628 (Fax: x-5200) |
| Department of Electrical and Computer Engineering | CCT Office: | +1 225-578-8979 (Fax: x-5362) |
| and Center for Computation and Technology (302 Johnston Hall) | ECE Dept.: | +1 225-578-5241 |
| Louisiana State University, Baton Rouge, LA 70803-5901, USA | E-mail: | j x r {@} ece.lsu.edu |
| Quick Links |
Teaching - Fall 2012: EE 4702: High-Level Synthesis and Embedded Systems
Teaching - Spring 2012: EE 4702: Software Optimizations
| Research |
| Research Interests |
Compiler optimizations for high performance computers: GPUs, multicore, accelerators. Embedded systems: compilers, design, processors Parallel computing: architecture, algorithms, software Computer architecture Compilers, operating systems and architectures for low power Hardware synthesis and optimization: behavioral-level, logic-level
| Current and Recent Research Grants |
« National Science Foundation Computing Research Infrastraucture (CRI) grant: Shelob - A Heterogeneous Computing Platform to Enable Transformation of Computational Research and Education in the State of Louisiana, 2012-15 « National Science Foundation grant: Research Software Infrastructure for Tensor Computations, 2011-14 « National Science Foundation Major Research Infrastraucture (MRI) grant: MRI: Development of Melete: an interaction-oriented, software-rich compute cluster with tangible interface support for collaborative research and the classroom, 2011-15 « National Science Foundation Louisiana EPSCoR Research Infrastructure Improvement grant: Louisiana Alliance for Simulation-Guided Materials Applications (LASiGMA), 2010-15 (Team Lead for LSU portion of Cyber Tools and Cyber Infrastructure) « US Army Research Office contract: Compiler-Driven Performance Optimization and Tuning for Multicore Architectures, 2009-12 « NSF Strategic Technologies for Cyberinfrastructure (OCI STCI) grant: An Environment for Portable High Productivity High Performance Computing on GPUs/Accelerators, 2009-12 « NSF Computing Processes and Artifacts (CISE CCF) Compilers grant: An Effective Automatic Parallelization Framework for Multi-Core Architectures, 2008-12
« NSF Computing Processes and Artifacts (CISE CCF) Compilers grant: Search-Based Model-Driven Framework for Compiler Optimizations, 2006-11 « NSF Computer Systems Research (CISE CSR) grant: CSR-AES: An Integrated Framework for Compile-time/Run-time Support for Multi-Scale Applications on High-End Systems, 2005-09 « NSF Nanoscale Exploratory Research grant: NER: Integration of Ab-Initio Computation with Large Scale Molecular Dynamics Simulation for Nanomaterials Research, 2005-07 « NSF Information Technology Research (ITR) grant: Synthesis of High Performance Algorithms for Electronic Structure Calculations, 2001-07
| Software |
PLUTO - An automatic parallelizer and locality optimizer for multicores Download PLUTO
CUDA version of PLUTO: Download Pluto 0.6.2-CUDA (BETA)
PrimeTile -- A parametric multi-level tiler for imperfect loop nests PrimeTile website Download PrimeTile
| Publications |
h-index: 36. g-index: 55.
Recent Publications (most in pdf)
Full List of Publications (some pdf included)
Publications (from Google Scholar)
Recent Articles (from Google Scholar)
Publications (from the new DBLP)Selected Recent Publications
- L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam and P. Sadayappan, "Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework," in Proc. ACM/IEEE Conference on High Performance Computing SC10, New Orleans, LA, November 2010.
- M. Baskaran, A. Hartono, S. Tavarageri, T. Henretty, J. Ramanujam, and P. Sadayappan, "Parameterized Tiling Revisited," International Symposium on Code Generation and Optimization (CGO), Toronto, Canada, April 2010.
- M. Baskaran, J. Ramanujam, and P. Sadayappan, "Automatic C-to-CUDA Code Generation for Affine Programs," International Conference on Compiler Construction (CC), Paphos, Cyprus, March 2010.
- Q. Lu, C. Alias, U. Bondhugula, T. Henretty, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, Y. Chen, H. Lin, T. Ngai, "Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors," Proc. Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, September 2009.
- A. Hartono, M. Baskaran, C. Bastoul, A. Cohen, S. Krishnamoorthy, B. Norris, J. Ramanujam, and P. Sadayappan, "Parametric multi-level tiling of imperfectly nested loops," ACM International Conference on Supercomputing (ICS), New York, NY, June 2009.
- M. Baskaran, N. Vydhyanathan, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "Compiler-Assisted Dynamic Scheduling for Effective Parallelization of Loop Nests on Multicore Processors," in Proc. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, NC, February 2009.
- A. Hartono, Q. Lu, T. Henretty, S. Krishnamoorthy, H. Zhang, G. Baumgartner, D. E. Bernholdt, M. Nooijen, R. Pitzer, J. Ramanujam, and P. Sadayappan, "Performance Optimization of Tensor Contraction Expressions for Many-Body Methods in Quantum Chemistry," The Journal of Physical Chemistry A, Vol. 113 (45), pp. 12715-12723, 2009.
- Hassan Salamy and J. Ramanujam, "A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip," in Proc. 4th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC 2009), Paphos, Cyprus, January 2009.
- M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "A compiler framework for optimization of affine loop nests for GPGPUs," ACM International Conference on Supercomputing (ICS), June 2008.
- U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, "PLUTO: A Practical and Fully Automatic Polyhedral Program Optimization System," Proc. ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation (PLDI 08), Tucson, AZ, June 2008.
- U. Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan, "Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model," in Proc. CC 2008 - International Conference on Compiler Construction, March-April 2008.
- M. Baskaran, U. Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev and P. Sadayappan, "Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories," in Proc. 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (PPoPP 2008), Salt Lake City, UT, February 2008.
- H. Salamy and J. Ramanujam, "Optimal Address Register Allocation for Arrays in DSP Applications," in Proc. 6th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2008), pp. 67–72, Atlanta, GA, October 2008.
- H. Salamy and J. Ramanujam, "Storage Optimization through Code Size Reduction for Digital Signal Processors," in Proc. 6th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2008), pp. 107–112, Atlanta, GA, October 2008.
- J. Hong and J. Ramanujam, "Scheduling DAGs for Fixed-point DSP Processors by Using Worm Partitions," in Proc. 2008 International Conference on Embedded Systems and Software (ICESS-08), pp. 567–574, Chengdu, China, July 2008.
- S. Krishnamoorthy, M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev and P. Sadayappan, "Effective Automatic Parallelization of Stencil Computations," in Proc. ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation (PLDI 07), San Diego, CA, June 2007.
- U. Bondhugula, J. Ramanujam, and P. Sadayappan, "Automatic Mapping of Nested Loops to FPGAs," in Proc. ACM SIGPLAN 2007 Symposium on Principles and Practice of Parallel Programming (PPoPP 07), San Jose, CA, March 2007.
- J. Ramanujam, J. Hong, M. Kandemir, A. Narayan, and A. Agarwal, "Estimating and Reducing the Memory Requirements of Signal Processing Codes for Embedded Processor Systems," IEEE Transactions on Signal Processing, vol. 54, no. 1, pp. 286--294, January 2006.
- G. Baumgartner, A. Auer, D. Bernholdt, A. Bibireata, V. Choppella, D. Cociorva, X. Gao, R. Harrison, S. Hirata, S. Krishnamoorthy, S. Krishnan, C. Lam, Q. Lu, M. Nooijen, R. Pitzer, J. Ramanujam, P. Sadayappan, and A. Sibiryakov, "Synthesis of High-Performance Parallel Programs for a Class of ab initio Quantum Chemistry Models," Proceedings of the IEEE, vol. 93, no. 2, pp. 276-292, February 2005.
- X. Gao, S. Sahoo, Q. Lu, G. Baumgartner, C. Lam, J. Ramanujam, and P. Sadayappan, "Performance Modeling and Optimization of Parallel Out-of-Core Tensor Contractions," in Proc. ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming, Chicago, IL, June 2005.
- S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C. Lam, J. Ramanujam, P. Sadayappan, and V. Choppella, "Efficient Synthesis of Out-of-Core Algorithms Using a Nonlinear Optimization Solver," Journal of Parallel and Distributed Computing, vol. 66, no. 5, pp. 659-673, May 2006. An ealier version appears as: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C.-C. Lam, J. Ramanujam, and P. Sadayappan, "Efficient Synthesis of Out-of-core Algorithms Using a Nonlinear Optimization Solver," In Proceedings of the 18th International Parallel and Distributed Processing Symposium (2004 IPDPS Conference), April 2004. (Best Paper Award)
| Research Links |
LSU Rainmaker, 2008; 2009.
Ritter Distinguished Professor of Electrical Engineering, 2005-present.
Best Paper Award (Applications Track) for "Efficient Synthesis of Out-of-core Algorithms Using a Nonlinear Optimization Solver," (authors: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C. Lam, J. Ramanujam, and P. Sadayappan) at the 18th International Parallel and Distributed Processing Symposium (2004 IPDPS Conference), Santa Fe, April 2004.
Best Paper Award (Systems) for "Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms," (authors: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, D. Cociorva, C. Lam, P. Sadayappan, J. Ramanujam, D. Bernholdt, and V. Choppella) at the International Conference on High Performance Computing (HiPC 03), December 2003.
Distinguished Visitor, IEEE Computer Society, 2001-2003.
NSF Young Investigator Award, 1994.
- Sameer AbuAsal
- Ye Fang
- Sahar Navaz
- Mohammad Rastegar Tohid
Tutorials and Workshops:
- Multicore Processors and GPUs: Programming Models and Compiler Optimizations, half-day tutorial (with P. Sadayappan) at 2012 International Symposium on Code Generation and Optimization (CGO), April 1, 2012 (PM session), San Jose, CA, USA.
- Multicore Processors and GPUs: Programming Models and Compiler Optimizations, half-day tutorial (with P. Sadayappan) at 20th International Conference on Parallel Architectures and Compilation Techniques (PACT), October 14, 2011, Galveston Island, TX, USA.
- GPUs and General-Purpose Multicores: Programming Models, Compiler Optimization and Tuning, half-day tutorial (with P. Sadayappan) at 25th International Conference on Supercomputing, June 4, 2011, Tucson, Arizona, USA
- WOLFHPC: Workshop on Domain-Specific Languages and High-Level Frameworks for High-Performance Computing, workshop (co-organized with Sriram Krishnamoorthy and P. Sadayappan) at 25th International Conference on Supercomputing, May 31, 2011, Tucson, Arizona, USA
- GPU Programming Models, Optimizations and Tuning, half-day tutorial (with P. Sadayappan) at The International Symposium on Code Generation and Optimization, CGO 2011, April 2, 2011, Chamonix, France
Summer Schools:
Beyond the PC - Application specific systems: design and implementation, Ecole Normale Supérieure de Lyon, Lyon, France, February 15-19, 2010
ACACES 2009: Fifth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Terrassa (near Barcelona), Spain, July 12-18, 2009.
Call for Papers:
- Links to Conferences, Journals, ... (maintained by Chandra Krintz)
- Related Conferences for ParaMount Groups (maintained by ParaMount Group - Rudolf Eigenmann)
- Conferences and Workshops of Interest (maintained by Jaewook Shin)
- Future deadlines for events (old name = EDA/CAD list) (maintained by Dirk Stroobandt)
- Upcoming and Recent FPGA/VLSI/CAD Conferences (maintained by Steve Wilton)
- Microelectronic Systems News Calendar (maintained by Don Bouldin)
| Teaching |
| Fall 2012 |
Fall 2012: EE 4702: High-Level Synthesis and Embedded Systems
| Spring 2012 |
Spring 2012: EE 4702: Software Optimizations
| Recent Courses |
Local Links
Sights from around Baton Rouge (thanks to the Sociology Department)
Areas of Specialization from the College of Engineering Website
Department of Electrical and Computer Engineering (ECE at LSU)
Phone List ECE Department (at LSU)
College of Engineering, Louisiana State University (LSU)
Course Offerings: Louisiana State University (LSU)
Academic Calendars: Louisiana State University (LSU)
Final Exam Schedule: Louisiana State University (LSU)