EE 4702: High-Level Synthesis

Fall 2003 - Call Number: 1823

Course material (handouts, ...)

Title:                EE 4702: High-Level Synthesis

Call No.:          1823

Professor:       J. (Ram) Ramanujam, 345 EE Bldg., 578-5628    Email:

Office Hours:   MWF 8:30 - 9:40; MWF 11:30 - 12:00

Time:                9:40 - 10:30 MWF, 145 EE Building NOTE ROOM CHANGE

Grader:            Ankush Agarwal, Desk G57, Room 150 EE.

Textbook:      None; Class notes.

References:

• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, 1994.
• High-Level Synthesis: Introduction to Chip and System Design,
         D. Gajski, N. Dutt, A. Wu and S. Lin, Kluwer, 1992.
• Logic Synthesis, S. Devadas, A. Ghosh, and K. Keutzer, McGraw-Hill, 1992.
• Introduction to Algorithms, T. Cormen, C. Leiserson, R. Rivest, MIT Press, 1990.

Prerequisites: CSC 3102 and credit/registration in EE 3755. Background in VLSI or compilers not needed.

Description

The course deals with synthesis and optimization of large scale digital systems primarily at the architectural level, starting from a high-level specification. We will also take a look at the effect of compiler transformations on design quality. System-level (hardware and software) design issues will also be discussed. We will discuss relevant graph algorithms for scheduling and other problems in synthesis, along with a discussion of good lower and upper bounds for problems. This course covers topics in an important emerging area in digital design.

Course Topics:  A large subset of these will be covered

• Introduction: digital synthesis, application-specific ICs.
• Background in areas such as graph algorithms (depth-first and bread-first search, shortest path, interval graphs), combinatorial optimization (integer linear programming, problem formulation, bounds) , etc.
• High-level synthesis of data-flow and control units from architectutal specifications:
  • clock selection; module selection; resource allocation
  • operation scheduling and register binding
  • register and memory synthesis
  • power optimizations
  • design space exploration
• Compiler/software optimization: program analysis and transformations.
• Memory estimation and design
• System-level synthesis; hardware-software co-design.

Grading:

• Homework, Programs, Presentation/Project (30%)
• Best 2 of 3 tests (20% each)
• Final (30%): Dec. 12, 2003