Fall 2008        EE 7785: Parallelizing Compilers
 T Th 9:10-10:30                            Professor: J. (Ram) Ramanujam

Course Information:

Instructor: J. (Ram) Ramanujam, 345 EE Bldg., 578-5628 (jxr at ece.lsu.edu)
Time, Place: T Th 9:10- 10:30 in room 149 EE Building
Office Hours: Mon.: 9:00-11:00; T,Th: 10:45-12:15
Text: None; Papers and class notes
Reference: High Performance Compilers for Parallel Computing, M. Wolfe, 1996
  Optimizing Compilers for Modern Architectures, R. Allen and K. Kennedy, 2002
Prerequisites:   Graduate standing
Goals: To familiarize the student with techniques used in optimizing compilers for a variety
of architectures, including high-performance architectures

Catalog Data:

7785 Parallelizing Compilers (3)  Prerequisites: Graduate standing. Analysis and optimization of programs for a variety of architectures; impact on architectural design.

Description:

The course deals with principles and practice of compiler optimizations, in particular source-to-source transformations. Programming paradigms, compiler support and their relation to high-performance architectures will be discussed. The issues of dependence analysis, program transformations, data locality, scheduling, synchronization and communication will be covered in the context of a variety of machine architectures.

Course Outline:

  1. Review of high-performance computing:
    • architectural taxonomy, modern processor architectures
    • synchronization, latency, partitioning
  2. Techniques for Parallelism Detection:
    • dependence analysis; value-based dependence
    • integer programming based dependence tests
    • dependence test hierarchy; engineering dependence testing
  3. Program Restructuring:
    • standard transformations, vectorization
    • parallelization, synchronization, loop fusion and scalarization
    • reductions and recurrences, loop scheduling
    • loop interchange and skewing, wavefront transformation
    • unimodular and non-unimodular transformations
    • unified framework for transformations
    • systolic transformations
    • iteration space tiling
    • communication optimizations
    • program transformations for data locality and memory hierarchy
    • analysis and optimization of non-array codes
    • compiling for different parallel architectures
    • compilation for accelerators: FPGAs, Cell-like architectures, GPUs
    • code generation and optimization for explicitly managed memory hierarchies
    • impact of transformations on architectural design
  4. Additional Topics (will be covered if we have time):
    • control flow graph, dominators, interval analysis, dataflow analysis
    • program dependence graph, single assignment form
    • inter-procedural analysis and optimizations

Grading : TWO tests (20% each), a final (30%), term-paper, projects and class presentation (30%).

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