EE 7000-6: High-Level Synthesis
MWF 7:40 - 8:30                              Spring 2006
Course Handouts and Other Material
Title: EE 7000-6: High-Level Synthesis Professor: J. (Ram) Ramanujam, 345 EE Bldg., 578-5628 (Email: jxr [at] ece [dot] lsu [dot] edu) Time and Place:   7:40 - 8:30 MWF, room 149 Elec. Engr. Bldg. Text:
Class notes and recent papers from the literature. NO REQUIRED TEXT References:
1.  Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, 1994.
2.  High-Level Synthesis: Introduction to Chip and System Design, D. Gajski, N. Dutt, ..., Kluwer, 1992.
3.  Introduction to Algorithms, T. Cormen, C. Leiserson, R. Rivest, MIT Press, 1990.
Prerequisites:   Graduate standing. No need for
background in VLSI or compilers. Goals: To familiarize s
tudents with the techniques used in high-level synthesis
The course deals with synthesis and optimization of large scale
digital systems primarily at the architectural level, starting from a
high-level specification. We will also take a look at the effect of
compiler transformations on design quality. System-level (hardware
and software) design issues will also be discussed.
We will discuss relevant graph algorithms for scheduling and other
problems in synthesis, along with a discussion of good lower and
upper bounds for problems.
This course covers topics in an important emerging area in digital design.