Spring 2010

DESIGN ELECTIVE for both EE and EEC students

EE 4702: High-Level Synthesis and Embedded Systems

M W 5:10 pm - 6:30 pm, 145 EE Building

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Course material (handouts, ...)

Title:                    EE 4702: High-Level Synthesis and Embedded Systems

Professor:          J. (Ram) Ramanujam, 345 EE Bldg., 578-5628 (Email: jxr AT ece DOT lsu DOT edu)

Office Hours:     Mon, Wed 8:30am-10:30am; 4:40pm-5:10pm  

Time/Place:        5:10 - 6:30 M W 145 EE Building

Textbook:           None; Class notes.
References:

• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, 1994.
• High-Level Synthesis: Introduction to Chip and System Design, D. Gajski, N. Dutt, A. Wu and S. Lin, Kluwer, 1992.
• Computers as Components: Principles of Embedded System Design, Wayne Wolf, Morgan Kaufmann, 2001.
• Embedded System Design, Peter Marwedel, Springer, 2005. (Hardcopy edition 2003).

Prerequisities:    (CSC 1254 or equivalent AND EE 2730 or equivalent) OR permission of instructor.

 

Description

The course deals with synthesis and optimization of large scale digital systems primarily at the architectural level, starting from a high-level specification. We will also take a look at the effect of compiler transformations on design quality. System-level (hardware and software) design issues will also be discussed. We will discuss relevant graph algorithms for scheduling and other problems in synthesis, along with a discussion of good lower and upper bounds for problems. This course covers topics in an important emerging area in digital design.

Course Topics:  A large subset of these will be covered

• Introduction: digital synthesis, application-specific ICs.
• Background in areas such as graph algorithms (depth-first and bread-first search, shortest path, interval graphs), combinatorial optimization (integer linear programming, problem formulation, bounds) , etc.
• Hardware description languages (unlikely)
• High-level synthesis of data-flow and control units from architectural specifications:
  • clock selection; module selection; resource allocation
  • operation scheduling and register binding
  • register and memory synthesis
  • design space exploration
• Embedded systems:
• Compiler/software optimization for embedded systems: program analysis.
• Compiler/software optimization for embedded systems: transformations.

Grading:

• Homework, Programs, Presentation/Project (30%)
• 2 tests (20% each)
• Final (30%)