LCPC 2005:

The 18th International Workshop on Languages and Compilers
for Parallel Computing

October 20-22, 2005
Hawthorne, New York, USA

LCPC 2005 Program

Thursday, October 20, 2005

8:30-9:00am Welcome
9:00-10:30am Session 1: Register Optimization
Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms
Authors: Keith Cooper, Anshuman Dasgupta, and Jason Eckhardt
Paper, Slides
Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design
Authors: Alban Douillet, Hongbo Rong, and Guang R. Gao
Paper, Slides
Manipulating MAXLIVE For Spill-Free Register Allocation
Authors: Shashi Deepa Arcot, Henry Dietz, and Sarojini Priyadarshini Rajachidambaram
Paper, Slides
10:30-11:00am Coffee Break
11:00-12:30pm Session 2: Compiling for FPGA's and Network Processors
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Authors: Tao Liu, Xiao-Feng Li, Lixia Liu, and Chengyong Wu
Paper, Slides
Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures
Authors: Heidi E. Ziegler, Priyadarshini L. Malusare, and Pedro C. Diniz
Paper, Slides
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code
Authors: David C. Zaretsky, Gaurav Mittal, Robert Dick, and Prith Banerjee
Paper, Slides
12:30-1:30pm Lunch
1:30-3:30pm Session 3: Model-Driven and Empirical Optimization - I
Applying Data Copy To Improve Memory Performance of General Array Computations
Author: Qing Yi
Paper, Slides
A Cache-conscious Profitability Model for Empirical Tuning of Loop Fusion
Authors: Apan Qasem and Ken Kennedy
Paper, Slides
Optimizing Matrix Multiplication with a Classifier Learning System
Authors: Xiaoming Li and Maria Jesus Garzaran
Paper, Slides
A Language for the Compact Representation of Multiple Program Versions
Authors: Sebastien Donadio, James Brodman, Thomas Roeder, Kamen Yotov, Denis Barthou, Albert Cohen, Maria Jesus Garzaran, David Padua, and Keshav Pingali
Paper, Slides
3:30-4:00pm Coffee Break
4:00-6:00pm Session 4: Parallel Languages
Efficient Computation of May-Happen-in-Parallel Information for Concurrent Java Programs
Author: Rajkishore Barik
Paper, Slides
Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-aware Compiler
Authors: Chi-Leung Wong, Zehra Sura, Xing Fang, Kyungwoo Lee, Samuel P. Midkiff, Jaejin Lee, and David Padua
Paper, Slides
Concurrency Analysis for Parallel Programs with Textually Aligned Barriers
Authors: Amir A. Kamil and Katherine A. Yelick
Paper, Slides
Titanium Performance and Potential: an NPB experimental study
Authors: Kaushik Datta, Dan Bonachea, and Katherine Yelick
Paper, Slides

Friday, October 21, 2005

9:00-10:00am Keynote talk
10:00-10:30am Coffee Break
10:30-12:30am Session 5: Model-Driven and Empirical Optimization - II
Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations
Authors: Xiaoyang Gao, Sriram Krishnamoorthy, Swarup Kumar Sahoo, Chi-Chung Lam, Gerald Baumgartner, J. Ramanujam, and P. Sadayappan
Paper, Slides
Automatic Measurement of Instruction Cache Capacity
Authors: Kamen Yotov, Sandra Jackson, Tyler Steele, Keshav Pingali, and Paul Stodghill
Paper, Slides
Combined ILP and Register Tiling: Analytical Model and Optimization Framework
Authors: Lakshminarayanan Renganarayana, U. Ramakrishna, and Sanjay Rajopadhye
Paper, Slides
Analytic Models and Empirical Search: A Hybrid Approach to Code Optimization
Authors: Arkady Epshteyn, Maria Garzaran, Gerald DeJong, David Padua, Gang Ren, Xiaoming Li, Kamen Yotov, and Keshav Pingali
Paper, Slides
12:30-1:30pm Lunch
1:30-3:00pm Session 6: Speculative Execution
Testing Speculative Work in a Lazy/Eager Parallel Functional Language
Authors: Alberto de la Encina, Ismael Rodriguez, and Fernando Rubio
Paper, Slides
Loop Selection for Thread-Level Speculation
Authors: Shengyue Wang, Xiaoru Dai, Kiran S Yellajyosula, Antonia Zhai, and Pen-Chung Yew
Paper, Slides
Software Thread Level Speculation for the Java Language and Virtual Machine Environment
Authors: Christopher J. F. Pickett and Clark Verbrugge
Paper, Slides
3:00-3:15pm Coffee Break
3:15-4:45pm Session 7: Run-time Environments
Lightweight Monitoring of the Progress of Remotely Executing Computations
Authors: Shuo Yang, Ali R. Butt, Y. Charlie Hu, and Samuel P. Midkiff
Paper, Slides
A Platform to Use Hardware Performance Counters for Dynamic Compilation
Authors: Florian Schneider and Thomas R. Gross
Paper, Slides
A Domain-Specific Interpreter for Parallelizing a Large Mixed-Language Visualisation Application
Authors: Karen Osmond, Olav Beckmann, Anthony J. Field, and Paul H. J. Kelly
Paper, Slides
4:45-5:00pm Coffee Break
5:00-6:30pm Panel /Special Session
6:30-9:00pm Dinner

Saturday, October 22, 2005

9:00-11:00am Session 8: Compile-Time Analysis
Compiler Control Power Saving Scheme for Multi Core Processors
Authors: Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara
Paper, Slides
Code Transformations for One-Pass Analysis
Authors: Xiaogang Li and Gagan Agrawal
Paper, Slides
Scalable Arrays SSA and Array Data Flow Analysis
Authors: Guobin He, Silvius Rus, and Lawrence Rauchwerger
Paper, Slides
Interprocedural Symbolic Range Propagation for Optimizing Compilers
Authors: Hansang Bae and Rudolf Eigenmann
Paper, Slides
11:00-11:30am Coffee Break
11:30-12:30pm Session 9: Short Papers - I
Phase-based Parallelization of Utility Programs
Authors: Xipeng Shen and Chen Ding
Paper, Slides
A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization
Authors: Chun Chen, Jacqueline Chame, Mary Hall, and Kristina Lerman
Paper, Slides
An Efficient Approach for Self-Scheduling Parallel Loops on Multiprogrammed Parallel Computers
Authors: Arun Kejariwal, Alexandru Nicolau, and Constantine D. Polychronopoulos
Paper, Slides
12:30-1:30pm Lunch
1:30-2:30pm Session 10: Short Papers - II
Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications
Authors: Seung Woo Son, Guangyu Chen, Mahmut Kandemir, and Alok Choudhary
Paper, Slides
Supporting SELL for High-Performance Computing
Authors: Bjarne Stroustrup and Gabriel Dos Reis
Paper, Slides
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Authors: Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, and Jenq-Kuen Lee
Paper, Slides
2:30-2:45pm Closing Remarks

To LCPC 2005 Home Page

IBM Rsearch Universitat Politecnica de Catalunya Louisiana State University Ohio State University Springer Lecture Note Series

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