Information on the lectures given in class are listed below,
divided into roughly one-week sets. Information includes
when the lectures where given, and where applicable,
links to slides used in class. When possible
material will be added before it is used in class.
If material is not yet available see
lectures from last year.
Zoom Recording of 14 September 2020 LectureDescriptive styles (explicit structural, etc). Synthesis steps (elaborate, infer, technology mapping, etc), Cadence Genus commands, and samples of Verilog code reflecting state of design at each step.
Zoom Recording of 16 September 2020 LectureFinished synthesis overview, with a look at an "a+b>120" module. Started synthesis of combinational logic. Covered synthesis of arithmetic expressions and Boolean and bitwise expressions. Conversion of integers (or bit vectors) to Boolean values. Synthesis of the conditional operator (s?a:b) and the index operators (a[n]), for both multiplexors are inferred. Bit widths of intermediate values (self-determined and context-determined expression context) (and the a + b < 120 surprise).
Zoom Recording of 23 September 2020 LectureDynamic and associative arrays. Start of elaboration and generate material. Elaboration time constants. Generate statements and their difference with procedural code. Use of generate statements for iterative (linear) structures and for using recursion to describe tree-structured hardware.
Zoom Recording of 25 September 2020 LectureUsing generate statements to describe a ripple adder. Using generate statements to describe tree structures array sum (simple_tree) and array minimum (min_t). Start of the FF1 (find first one) example problem. (Similar to 2019 HW 2.)
Zoom Recording of 2 October 2020 LectureThe simple cost and performance model. Definition for 2-input AND and OR gates. Derived costs for commonly used structures including edge-triggered flip-flop, multiplexors, and ripple structures. Cascaded ripple structures.
Zoom Recording of 30 November 2020 LectureFinished 2019 Homework 6 (add_accum), and Problem 4a from the 2019 Final exam which asks about synthesis data for add_accum. Started the integer compression module, icomp.