EE 4755, Digital Design Using HDLs
When / Where / Details
Lecture slides and examples used in class.
The current status of the computers in
Room 2241 P.F. Taylor Hall. Updated every 10 minutes.
Instructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
Software manuals and information on Verilog.
Additional material on Verilog inference and synthesis.
The most accessed Web pages for this course over the
past three days.
Includes solutions. |
What's New
7 October 2026, 14:13:23 CDT
The deadline for Homework 2 is now Monday evening,
12 October 2026. Material on the logarithmic shifter is
linked to the lectures page under "Additional Material" for
Set 1. Material on the CLZ module is in 2019 Homwork 1.
30 September 2026, 14:25:01 CDT
TL;DR: The Homework 2 Verilog file has been updated but you don't need
to copy it if you have the old one. The Homework 2
Handout has also been updated, explaining the cw_itof issues
and benefiting from some more proofreading.
In class today I suggested that the cw_itof module
we used to compare to our own module tiger_itof might have
had
higher cost because cw_itof instantiated a left-justify
module that was only needed for testbench compabitility. The synthesis
program should have optimized out the left-justify module, and it
did. Nevertheless the hw02.v now hides the left-justify
module so we can be absolutely sure the cw_itof cost
reflects only the Chipware module.
29 September 2026, 19:39:34 CDT
Homework 2 assigned, due Wednesday, 7
October 2026.
What Was New
10 more items starting 25 September 2026, 15:54:47 CDT.
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