EE 4755 - What's New

15 December 2015, 9:07:07 CST
Grading Update 6: Final grades submitted. Since many people reading this already know their letter grades I won't be putting them on the grades page. Have a good break!

14 December 2015, 18:12:11 CST
Grading Update 5: Homework grades and course average has been added to the grades page. I haven't decided course grades yet, that might not be available until tomorrow. The next grading update will be posted about 9:00 tomorrow.

14 December 2015, 16:59:22 CST
Grading Update 4: The last homework assignment is almost completely graded. (Those grades will be E-mailed.) After that final averages will be posted, possibly along with letter+sign grades. If letter grades aren't posted soon take solace in the fact that the longer I wait the less strict and more understanding I get. The next grading update will be posted by 20:00 tonight.

14 December 2015, 13:29:56 CST
Grading Update 3: Final Exam Grades Ready One person came within two points of a perfect score. The average is 51.7, the range [98,8]. Where are you? To find out, or just to look at the aliases, click here. Final averages will be available later today, and possibly course grades too. The next grading update will be posted about 17:00.

14 December 2015, 11:58:35 CST
Grading Update 2: Problems 1-5 graded. Final exam grades will be available in an hour or two. The next grading update will be posted by 14:00.

13 December 2015, 16:01:04 CST
Grading Update 1(late): Problem 1 partially graded. Final exam grades will be available some time tomorrow. The next grading update will be posted about noon tomorrow.

12 December 2015, 15:45:10 CST
Grading Update 0: Final exam grading will start late this afternoon or tomorrow. The final exam grades may be available tomorrow, don't expect course grades to be ready until Monday late afternoon at the earliest. The next grading update will be posted tomorrow about 13:00.

10 December 2015, 19:27:29 CST
Linked the Verilog source for the integer compression and CAM modules to the lectures page.

8 December 2015, 16:11:12 CST
Linked the Homework 6 solution and solution Verilog code to the assignments and exams page.

4 December 2015, 13:13:24 CST
Linked final exam review slides to the lectures page. Additional material will be posted between now and the final exam.

23 November 2015, 15:16:49 CST
The deadline for Homework 6 changed to Wednesday night, 2 December 2015.

20 November 2015, 18:56:45 CST
Homework 6 assigned, due Monday night, 30 November 2015.

2 November 2015, 18:15:49 CST
Linked the midterm exam and solution to the assignments and exams page.

1 November 2015, 10:06:42 CST
Grading Update 4:Midterm exam grades ready. The range is [89,8] with a median of 57 and a mean of 54. The standard deviation is 21.4. To find out where you stand click here.

31 October 2015, 17:43:37 CDT
Grading Update 3: Grades will be posted tomorrow before noon. The next grading update will be posted by 11:00 CST tomorrow. Happy Halloween!

30 October 2015, 17:30:59 CDT
Grading Update 2: Just started grading Problem 1. There is a chance the grades will be ready by tomorrow. The next grading update will be posted by 18:00 tomorrow.

29 October 2015, 17:16:50 CDT
Grading Update 1: Grading should start on Friday and grades may be available on Saturday. The next grading update will be posted by 18:00 tomorrow.

28 October 2015, 15:31:03 CDT
Grading Update 0: Grading should begin some time tomorrow or Friday. Grades should be available before Monday. Have a good Fall Holiday!

25 October 2015, 17:23:32 CDT
Updated the stream_3 module diagram in the Homework 5 solution. The enable signal for the prod register should be connected to pos==1 logic.

25 October 2015, 14:17:31 CDT
Linked the Homework 5 solution to the assignments and exams page.

24 October 2015, 19:54:57 CDT
Linked the Homework 4 solution to the assignments and exams page. Pay attention to the solution to Problem 2b.

23 October 2015, 15:19:05 CDT
Linked the midterm exam review slides to the lectures page. Solutions to Homework 4 and 5 will be posted before the end of the weekend.

21 October 2015, 17:32:13 CDT
For Homework 5 use 10 units for the latch delay. This delay was omitted from the original assignment but is now included.

21 October 2015, 12:44:33 CDT
Linked multiplier Verilog code to the lectures page.

16 October 2015, 18:41:55 CDT
Homework 5 assigned, due Friday, 23 October 2015 at 17:00..

12 October 2015, 11:11:17 CDT
Linked the Homework 3 solution to the assignments and exams page.

9 October 2015, 12:41:02 CDT
Homework 4 deadline moved to the evening of Monday, 12 October 2015. Hint: To debug run the Verilog simulator using the gui: "irun hw04.v -gui". An introduction to the GUI tool is available from on campus. Additional documentation can be accessed using the command cdnshelp.

7 October 2015, 18:17:52 CDT
Linked the Homework 2 solution to the assignments and exams page. Don't forget that Homework 3 is due today and Homework 4 is due FridayMonday.

2 October 2015, 18:32:03 CDT
Homework 3 and Homework 4 assigned, they are due Wednesday, 7 October and Friday, 9 October 2015Monday, 12 October, respectively. Homework 3 is paper-only, Homework 4 requires running Verilog simulation and synthesis programs. Those solving Homework 3 who want dazzling syntax-highlighted versions of the modules can get them in this HTMLized Homework 4 Verilog file. (The modules needed for Homework 3 are in the file for Homeowrk 4.) For best results, start early and ask for help if you need it.

2 October 2015, 16:01:40 CDT
Linked the event queue slides to the lectures page. The next homework assignments will be posted later today.

25 September 2015, 15:51:04 CDT
Linked the sequential logic synthesis classroom slides and the code samples to the lectures page.

18 September 2015, 15:43:24 CDT
Linked the combinational logic synthesis slides to the lectures page.

17 September 2015, 19:41:14 CDT
Linked a Synthesis study guide to the new study guides page.

16 September 2015, 15:04:15 CDT
Homework 2 Warning: Infinite recursion will cause the Verilog simulator to seem to hang and may leave your design database in a corrupted state. If this happens kill the compilation window or just exit Emacs. Make sure that min_t (1) only instantiates another min_t module if its input parameters are above some value and (2) that the min_t modules are instantiated with smaller values of some parameters.

11 September 2015, 15:00:09 CDT
Linked the Homework 1 solution to the assignments and exams page.

11 September 2015, 10:31:22 CDT
Linked code examples from class to the lectures page. This includes the population counter examples in which generate statements were used to construct linear connections and trees.

9 September 2015, 11:25:33 CDT
Homework 2 assigned, due Wednesday, 16 September 2015.

4 September 2015, 11:20:32 CDT
Homework 1 assigned, due Wednesday, 9 September 2015. Homework 2 will be assigned over the holiday weekend and will be due the 14th. Homework 1 does not require the use of Verilog implementations, but Homework 2 will.

21 August 2015, 13:18:52 CDT
Set up pages for Fall 2015 semester.

Fall 2014
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David M. Koppelman -
Modified 15 Dec 2015 9:11 (1511 UTC)