EE 4755, Digital Design Using HDLs


When / Where / Details

Fall 2018: MWF 9:30-10:20 CT Room 226 Tureaud Hall
Fall 2018 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in the back of Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

Assignments and Exams

Includes solutions.
Screenshot of design.
RSS Feed What's New
11 November 2018, 13:16:23 CST
Homework 7 assigned, due Friday, 16 November 2018. An additional assignment will be given based on the modules in Homework 7. Also expect to see some final exam questions based on this assignment.

10 November 2018, 18:29:11 CST
The next homework will be assigned some time tomorrow.

9 November 2018, 10:52:59 CST
Updated the sequential multiplier demo notes and posted pipelining and piplined multiplier demo notes on the lectures page.

What Was New
34 more items starting 29 October 2018, 15:51:58 CDT.



David M. Koppelman - koppel@ece.lsu.edu
Modified 11 Nov 2018 13:18 (1918 UTC)
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