EE 4755, Digital Design Using HDLs


When / Where / Details

Fall 2017: MWF 9:30-10:20 CT Room 225 Tureaud Hall
Fall 2017 Syllabus

Current Lectures

Lecture slides and examples used in class.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

Assignments and Exams

Includes solutions.
Screenshot of design.
RSS Feed What's New
19 November 2017, 15:45:25 CST
Homework 7 assigned, due 29 November 2017. Start early.

13 November 2017, 9:12:41 CST
Linked a solution to Homework 5 Problems 1 and 2 to the assignments and exams page.

10 November 2017, 17:12:08 CST
Added sequential multipliers, pipelining and pipelined multipliers, and other recent classroom material code/slides [tm] to the lectures page.

What Was New
31 more items starting 8 November 2017, 9:20:24 CST.


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David M. Koppelman - koppel@ece.lsu.edu
Modified 19 Nov 2017 15:46 (2146 UTC)