EE 4755, Digital Design Using HDLs


When / Where / Details

Fall 2018: MWF 9:30-10:20 CT Room 226 Tureaud Hall
Fall 2018 Syllabus

Current Lectures

Lecture slides and examples used in class.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

Assignments and Exams

Includes solutions.
Screenshot of design.
RSS Feed What's New
1 August 2018, 13:06:37 CDT
Set up pages for Fall 2018 semester.

Fall 2017
Fall 2017 What's New



David M. Koppelman - koppel@ece.lsu.edu
Modified 1 Aug 2018 13:06 (1806 UTC)
Provide Website Feedback  • Accessibility Statement