EE 4755, Digital Design Using HDLs
When / Where / Details
Lecture slides and examples used in class.
Instructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
Software manuals and information on Verilog.
Additional material on Verilog inference and synthesis.
10 December 2017, 12:17:36 CST
Grading Update 5: Course Grades Ready.
Depending on your personality type, either make sure no one is looking
or get someone to start taking a video of you, and then
click here. (You may need to press refresh, and you will definitely
have to scroll down.)
Have a good break!
9 December 2017, 18:42:21 CST
Grading Update 4: Final Exam Grades ready.
The median was 58, the range [93,14]. To find the most important
grade, click here. Course grades will be decided tomorrow.
8 December 2017, 18:02:40 CST
Grading Update 3: Problems 1-4 graded. Exam
grades will be available tomorrow, and possibly course grades.
Drive carefully tomorrow!
What Was New
44 more items starting 8 December 2017, 12:55:07 CST.