EE 4755 - Lectures

Information on the lectures given in class are listed below, divided into roughly one-week sets. Information includes when the lectures where given, and where applicable, links to slides used in class. When possible material will be added before it is used in class. If material is not yet available see lectures from last year.

• Midterm Exam Review
  Covered 21 October 2024
  Additional Material
  • 2023 Midterm Exam
  • 2023 Midterm Exam solution
  • 2022 Midterm Exam
  • 2022 Midterm Exam solution
  • 2021 Midterm Exam
  • 2021 Midterm Exam solution
  • EE 4755 Exams

• Final Exam Review
  Covered 10 Dec 2024
  Additional Material
  • 2023 Final Exam
  • Solution to 2023 Final Exam
  • 2022 Final Exam
  • Solution to 2022 Final Exam
  • 2021 Final Exam
  • Solution to 2021 Final Exam

• Set 1: Course Information and EDA Overview
  Covered 26, 28, 30 August 2024
  Additional Material
  • Right shift unit variations.

• Verilog Review
  Covered 4, 6 September 2024
  Additional Material
  • Using 2-input mux to build 4- and 8-input mux, from 2017 hw 1

• Set 010: Behavioral Code Basics
  Covered 6, 9, 13 September 2024
  

• Basic Simulation
  Covered 13, 16 September 2024
  

• Synthesis of Combinational Logic in Implicit Structural Code
  Covered 16, 18 September 2024
  

• Set 020: Objects and Data Types
  Covered 18, 20, 23, 25, 27 September 2024
  Additional Material
  • 2018 Homework 3: A sort2 module with mixed integer/FP keys.
  • Correct, but costlier-than-necessary solution worked out in class.
  • A lower-cost solution to 2018 Homework 3
  • Sample problem: use FP in linear interpolation module.
  • Solution

• Elaboration, Generate Statements
  Covered 30, September 2024, 2, 4 October 2024
  Additional Material
  • 2019 HW 2: Count Leading Zeros
  • 2019 HW 2 (clz) solution.
  • Recursive (tree) multiplexor descriptions.
  • 2018 Homework 5: Recursive description of Batcher sorter.
  • Homework 5 solution.

• Simple Cost and Performance Model
  Covered 4, 7, 9, 11 October 2024
  Additional Material
  • Timing and cost problems from 2017 Final Exam Problem 3 (big mux).
  • Solution to 2017 Final Exam
  • Timing and cost problems from 2016 Final Exam (problems 2 and 4, fcfs_fit and greedy_fit)
  • 2016 Final Exam Solution.
  • 2022 Midterm Exam Problem 3a, delay and critical path.
  • 2022 Midterm Exam Solution.

• Synthesis of Behavioral Combinational Logic Descriptions
  Covered 11, 14, 21 October 2024
  Additional Material
  • 2018 Homework 6 solution.
  • Problems 2, 3a, and 5 from the 2016 Midterm Exam
  • 2016 Homework 4 solution.

• Synthesis of Behavioral Sequential Logic Descriptions
  Covered 25, 30 October, 1, 4 November 2024
  Additional Material
  • Expanded versions of Verilog examples from slides.
  • Sequential Shifters
  • A collection of solved problems related to sequential logic, including the problems covered in class during the 2022 semester.

• Combinational v. Sequential v. Pipelined Multiplier Implementation
  Covered 4, 6, 8 November 2024
  

• Pipelining, Latency v. Throughput
  Covered 8 November 2024
  

• Sequential and Pipelined Multipliers and Sequential Code Examples
  Covered 11, 13 November 2024
  Additional Material
  • Pipelined multipliers and pipelining background.

• Sequential Code Example: Multi-Step (2016 FE Prob 1)
  Covered 13, 15 November 2024
  

• Sequential Code Example: acc_accum (2019 Homework 6)
  Covered 18, 20 November 2024
  

• Sequential Code Example: bit_keeper (2021 Homework 4)
  Covered 22, 25 November 2024
  

• Sample Problem: Content-Addressable Memory (CAM)
  Covered 25 November, 2 December 2024
  

• Homework 6 Solution
  Covered 4 December 2024
  Additional Material
  • Solution to 2023 Final Exam. See Problem 2.