| 8:30-9:00am |
Welcome |
| 9:00-10:30am |
Session 1: Register Optimization
|
|
Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs
and Callahan-Koblenz Algorithms |
|
Authors: Keith Cooper, Anshuman Dasgupta, and Jason
Eckhardt |
|
Paper,
Slides |
|
Register Pressure
in Software-Pipelined Loop Nests: Fast Computation and Impact on
Architecture Design |
|
Authors: Alban Douillet, Hongbo Rong, and Guang R.
Gao |
|
Paper,
Slides |
|
Manipulating MAXLIVE For Spill-Free
Register Allocation |
|
Authors: Shashi Deepa Arcot, Henry Dietz, and
Sarojini Priyadarshini Rajachidambaram |
|
Paper,
Slides |
| 10:30-11:00am |
Coffee Break |
| 11:00-12:30pm |
Session 2: Compiling for FPGA's and Network Processors |
|
Optimizing
Packet Accesses for a Domain Specific Language on Network Processors |
|
Authors: Tao Liu, Xiao-Feng Li, Lixia Liu, and
Chengyong Wu |
|
Paper,
Slides |
|
Array
Replication to Increase Parallelism in Applications Mapped to Configurable
Architectures |
|
Authors: Heidi E. Ziegler, Priyadarshini L. Malusare,
and Pedro C. Diniz |
|
Paper,
Slides |
|
Generation of
Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code |
|
Authors: David C. Zaretsky, Gaurav Mittal, Robert
Dick, and Prith Banerjee |
|
Paper,
Slides |
| 12:30-1:30pm |
Lunch |
| 1:30-3:30pm |
Session 3: Model-Driven and Empirical Optimization - I |
|
Applying
Data Copy To Improve Memory Performance of General Array Computations |
|
Author: Qing Yi |
|
Paper,
Slides |
|
A
Cache-conscious Profitability Model for Empirical Tuning of Loop Fusion |
|
Authors: Apan Qasem and Ken Kennedy |
|
Paper,
Slides |
|
Optimizing
Matrix Multiplication with a Classifier Learning System |
|
Authors: Xiaoming Li and Maria Jesus Garzaran |
|
Paper,
Slides |
|
A Language
for the Compact Representation of Multiple Program Versions |
|
Authors: Sebastien Donadio, James Brodman, Thomas
Roeder, Kamen Yotov, Denis Barthou, Albert Cohen, Maria Jesus Garzaran,
David Padua, and Keshav Pingali |
|
Paper,
Slides |
| 3:30-4:00pm |
Coffee Break |
| 4:00-6:00pm |
Session 4: Parallel Languages |
|
Efficient
Computation of May-Happen-in-Parallel Information for Concurrent Java
Programs |
|
Author: Rajkishore Barik |
|
Paper,
Slides |
|
Evaluating
the Impact of Thread Escape Analysis on a Memory Consistency Model-aware
Compiler |
|
Authors: Chi-Leung Wong, Zehra Sura, Xing Fang,
Kyungwoo Lee, Samuel P. Midkiff, Jaejin Lee, and David Padua |
|
Paper,
Slides |
|
Concurrency
Analysis for Parallel Programs with Textually Aligned Barriers |
|
Authors: Amir A. Kamil and Katherine A. Yelick |
|
Paper,
Slides |
|
Titanium
Performance and Potential: an NPB experimental study |
|
Authors: Kaushik Datta, Dan Bonachea, and Katherine
Yelick |
|
Paper,
Slides |
