EE 4755 - What's New


20 September 2018, 13:05:13 CDT
Linked Elaboration and Generate Statements demo slides to the lectures page.

18 September 2018, 12:50:05 CDT
Homework 3 assigned, due 25 September 2018.

12 September 2018, 14:01:37 CDT
Linked Set 020, Objects and Data Types to the lectures page.

11 September 2018, 15:44:22 CDT
Linked the Homework 1 solution to the assignments and exams page. Graded submissions have been E-mailed.

11 September 2018, 10:10:43 CDT
Improved the wording of Problem 2 in Homework 2. In particular was more careful about the use of sort2, which refers to a Verilog module, and two-element sorting network, which does not refer to any particular implementation.

7 September 2018, 16:12:56 CDT
Added Synthesis overview synthesis of combinational structural code demo notes to the lectures page. Also updated the synthesis software links on the references page.

7 September 2018, 9:24:05 CDT
Homework 2 assigned, due Wednesday, 12 September 2018..

1 September 2018, 17:50:54 CDT
Added a link to the Computer Status page to the course home page, and provided more details on how to find a suitable machine for homework assignments to the procedures page.

29 August 2018, 18:11:48 CDT
Linked Verilog review (set 005) and behavioral code basics to the lectures page.

29 August 2018, 9:17:56 CDT
Homework 1 assigned, due 5 September 2018.

29 August 2018, 8:59:16 CDT
Updated procedures, especially the instructions for synthesis, changing them from Cadence RTL Compiler (RC) to Cadence Genus.

27 August 2018, 10:50:29 CDT
Linked Verilog review to the lectures page. The 2017 Homework 1 assignment and solution can be found on the assignments and exams page.

20 August 2018, 15:04:13 CDT
Linked The first set of slides and the shifter demo to the lectures pages.

1 August 2018, 13:06:37 CDT
Set up pages for Fall 2018 semester.

Fall 2017
Fall 2017 What's New



David M. Koppelman - koppel@ece.lsu.edu
Modified 20 Sep 2018 13:06 (1806 UTC)
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