EE 4755 - What's New

19 November 2017, 15:45:25 CST
Homework 7 assigned, due 29 November 2017. Start early.

13 November 2017, 9:12:41 CST
Linked a solution to Homework 5 Problems 1 and 2 to the assignments and exams page.

10 November 2017, 17:12:08 CST
Added sequential multipliers, pipelining and pipelined multipliers, and other recent classroom material code/slides [tm] to the lectures page.

8 November 2017, 9:20:24 CST
Homework 6 assigned, due Monday, 13 November 2017.

6 November 2017, 18:12:46 CST
There was an error in file syn.tcl in the Homework 5 assignment package. It's been fixed, but if you copied the file before 18:09 6 November 2017 then edit syn.tcl and change hw05-sol.v to hw05.v in a line near the top.

3 November 2017, 18:28:31 CDT
Homework 5 assigned, due 10 November 2017.

29 October 2017, 17:27:18 CDT
Clarified the meaning of character in the Homework 4 handout. (It might be easier to think of a character as an integer.)

27 October 2017, 18:23:38 CDT
Homework 4 assigned, due 1 November 2017.

25 October 2017, 14:17:11 CDT
Linked sequential logic slides and code samples to the lectures page.

24 October 2017, 11:24:57 CDT
Grading Update 3: Midterm Exam Grades Ready The median is 62 and the range is a gaping [92,15]. To find out the most important grade, or just to enjoy the creative aliases, click here.

23 October 2017, 18:59:22 CDT
Grading Update 2: Problems 1-4 graded. Grades should be available tomorrow, maybe before noon. The next grading update will be posted by noon, with or without grades.

23 October 2017, 14:09:59 CDT
Grading Update 1: Linked the midterm exam solution to the assignments and exams page. Grading will start soon, and grades will probably be ready tomorrow, maybe tonight. The next grading update will be posted about 19:00 tonight.

16 October 2017, 13:16:55 CDT
Grading Update 0: Linked the midterm exam to the assignments and exams page. There is a small chance that the grades will be available today or tomorrow. Otherwise, they will be available some time next week.

13 October 2017, 10:36:56 CDT
Don't forget that the midterm exam is on Monday. Linked the midterm exam review to the lectures page. Also updated the partial solution to the 2016 final exam. Additional updates to study material may be posted today and over the weekend.

11 October 2017, 19:13:57 CDT
Linked a partial solution to the 2016 final exam (which is also a solution to Homework 3) to the assignments and exams page. This solution will be updated in the coming days.

4 October 2017, 14:39:31 CDT
The midterm exam date has been set to Monday, 16 October 2017.

4 October 2017, 14:38:04 CDT
Homework 3 deadline has been changed to Thursday, 5 October. Linked Homework 2 solution to the assignments and exams page.

3 October 2017, 10:06:03 CDT
Added a brief description of the simple cost and performance model to the Homework 3 handout.

29 September 2017, 9:17:07 CDT
Homework 3 assigned, due Wednesday, 4 October 2017. This is a paper assignment.

26 September 2017, 17:15:16 CDT
Linked the synthesis of combinational behavioral code notes to the lectures page.

21 September 2017, 17:29:35 CDT
Added Verilog debugging instructions to the procedures page.

21 September 2017, 13:08:11 CDT
Linked Elaboration and Generate Statements notes to the lectures page. Includes diagrams of the minimum module.

20 September 2017, 16:06:38 CDT
The homework assignment available before 16:06 today had a small error in the description of functions a(x) and ai(j). In both cases an a1 term was missing. The assignment has been corrected. The module interp_behav, which implements ai(j), was always correct.

19 September 2017, 14:26:27 CDT
Linked the Homework 1 solution to the assignments and exams page.

18 September 2017, 18:51:44 CDT
Homework 2 assigned, due 25 September 2017

11 September 2017, 14:25:11 CDT
Linked 2015 Homework 1, its solution, and data types to the lectures page.

8 September 2017, 15:47:28 CDT
Due to the lab closing at 16:00 on Friday for the weekend, Homework 1 will not be copied until 13:30 on Monday.

7 September 2017, 15:44:39 CDT
Some systems in the lab won't run synthesis, these are being fixed now. Visit the computer status page and find the column labeled "H", it's the last under the software group. Verilog won't work on hosts (first column) that have a non-blank entry under the H column. Thank you for your patience.

1 September 2017, 17:22:04 CDT
Linked synthesis overview notes and synthesis of combinational logic in structural code to the lectures page.

1 September 2017, 17:12:48 CDT
Homework 1 assigned, due Friday, 8 September 2017. This assignment requires the use of the computers in the ECE workstation lab. See the procedures page for instructions.

28 August 2017, 16:18:06 CDT
Linked shifter variations examples and review notes to the lectures page.

21 August 2017, 14:55:08 CDT
Linked first note set to the lectures page.

1 August 2017, 11:17:46 CDT
Set up pages for Fall 2017 semester.

Fall 2016
Fall 2016 What's New

ECE Home Page
David M. Koppelman -
Modified 19 Nov 2017 15:46 (2146 UTC)