Preliminary Program for RAW 2003
Nice,
Tuesday
April 22nd
2003
8.00 - 8.10: Opening Session
8.10 - 9.00: Opening Keynote
University
of Kaiserslautern, Germany
Title: "
Are we really ready for the
break-through ?"
9.00 - 10.00: Session I Architectures
University of California, Berkeley
Title: "Massively
Parallel Wireless Reconfigurable Processor Architecture and Programming."
Universita` di Bologna, Bologna, Italy
Politecnico di Torino, Torino, Italy
NVM-DP Department of STMicroelectronics CR&D
Agrate, Italy
Title: "
A
Reconfigurable Processor Architecture and Software Development Environment for
Embedded Systems."
Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva
Universidade Federal do Rio Grande do Norte, Brazil
Title: "X4CP32:
A Coarse Grain General Purpose Reconfigurable Microprocessor."
10.00 - 10.30: Coffee Break
10.30 - 12.10: Session IIa/IIb (Parallel Session)
NASA Ames Research Center, USA
University of Central Florida, USA
Title: "Evolutionary Fault Recovery in a
Virtex FPGA Using a Representation That Incorporates Routing."
University of South Brittany, Lorient, France
University of Massachusetts, Amherst, USA
Title: "
Targeting
Tiled Architectures in Design Exploration."
Clemson University, USA
Title: "
Reconfigurable
Mapping Functions for Online Architectures."
TIMA Laboratori, Grenoble Cedex - France
Budapest University of Technology and Economics,
Hungary
Title: "
Dependability
Analysis: a New Application for Run-Time Reconfiguration."
IMEC vzw, Belgium
Title: "
Designing
an Operating System for a Heterogeneous Reconfigurable SoC."
VTT Electronics, Oulu, Finland
INTRACOM SA, Peania, Attika, Greece
IMEC, Leuven, Belgium
Title: "
System-Level
Modeling of Dynamically Reconfigurable Hardware with SystemC."
RMIT University, Melbourne, Australia
Title: "
A
Polymorphic Hardware Platform."
Technical University of Cluj-Napoca, ROMANIA
Title: "
CREC:
A Novel Reconfigurable Computing Design Methodology."
Université
Montpellier II, France
Ecole Nationale Supérieure de l'Electronique et de
ses Applications, France
Title: "
Metrics
for Reconfigurable Architectures Characterization: Remanence and Scalability."
George Washington University, USA
SRC Computers Inc.
George Mason University, USA
Title: "
Performance
and Overhead in a Hybrid Reconfigurable Computer."
12.10 - 13.40: Lunch Break
13.40 - 15.00: Session IIIa/IIIb (Parallel Session)
LIRMM , France
Pontifícia Universidade Católica do Rio Grande do
Sul , Brazil
Title: "
Remote
and Partial Reconfiguration of FPGAs: tools and trends."
George Mason University, USA
The George Washington University, USA
Université de Nancy, France
Title: "
Automated
RTR temporal partitioning for reconfigurable embedded real-time system design."
Swiss Federal Institute of Technology (ETH)
Zurich, Switzerland
Title: "
Fast
Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing."
University of Ljubljana, Slovenija
Title: "
HW/SW
Codesign of the MPEG-2 Video Decoder."
Queen’s University Belfast, UK
Title: "
A
Programmable and Highly Pipelined PPP Architecture for GIGABIT IP over
SDH/SONET."
Nitin Srivastava, Jerry L. Trahan,
Ramachandran Vaidyanathan, and Suresh Rai
Louisiana State University, USA
Title: "
Adaptive
Image Filtering using Run-Time Reconfiguration."
University of Twente, the Netherlands
Title: "
Mapping
of DSP Algorithms on the MONTIUM Architecture."
15.00 - 15.30: Coffee Break
15.30 - 16.10: Keynote II
PACT XPP Technologies AG, Muenchen, Germany
Title: "Reconfigurable Processor Architectures
for Mobile Phones"
16.10 - 16.50: Session IV Parallelization
Techniques
University of Algarve, Portugal
SUNY- Geneseo, Geneseo, USA
16.50 - 18.00: Poster Session
NEC Corporation, Tokyo, Japan.
Title: "A
New Scalable and Reconfigurable Architecture for high Speed and Programmable
Routers."
Aristotle University of Thessaloniki, Greece
Title: "Applying
Optical Reconfiguration on ATM Switch Fabrics."
Tottori University of Environmental Studies,
Japan
Title: "An
Efficient Scaling-Simulation Algorithm of Reconfigurable Meshes by Meshes with
Partitioned Buses."
Indian Institute of Technology, Madras, India
Title: "A
Parallel Genetic Approach To The Placement Problem For Field Programmable Gate
Arrays."
Katholieke Universiteit Leuven, ESAT/COSIC,
Belgium
Title: "Hardware
Implementation of a Montgomery Modular Multiplier in a Systolic Array."
La Sapienza University of Rome, Italy
Title: "Power
Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP
Microprocessors."
Gael Rouvroy, Francois-Xavier Standaert,
Jean-Jacques Quisquater, Jean-Didier Legat
Universite catholique de Louvain, Belgium
Title: "Efficient
FPGA Implementation of Block Cipher MISTY1."
Alcatel Space, France
TéSA, France
Title: "Towards
generic satellite payloads : software radio."
Infineon Technologies AG, Austria
Title: "A
New Reconfigurable Architecture for Single Cycle Context Switching."
Infineon Technologies AG, Munich, Germany
Title: "An
Approach for Mixed Coarse Granular and Fine Granular Re-Configurable
Architectures."
University of New Brunswick, Canada
University of Victoria, Canada
Title: "Reconfigurable
Architecture Requirements for Co-Designed Virtual Machines."
University of Applied Sciences Nordhausen,
Germany
Title: "Modelling
Programmable Logic Devices and Reconfigurable, Microprocessor-related
Architectures."
Kyushu Institute of Technology, Japan
Title: "An
Optically Differential Reconfigurable Gate Array with dynamic reconfiguration
circuit."
Visvanathan Subramanian, Joseph G.
Tront, Charles W. Bostian, Scott F. Midkiff
Virginia Tech, USA
Title: "Design
and Implementation of a Configurable Platform for Embedded Communication
Systems."
University of Paderborn, Paderborn, Germany
Title: "A
High Performance VLIW Processor for Finite Field Arithmetic."
Miroslav Lícko, Jan Schier, Zdenek
Pohl, Jirí Kadlec, Milan Tichý, Rudolf Matoušek, Antonín Hermánek
Institute of Information Theory and Automation,
Academy of Sciences of the Czech Republic
Title: "Logarithmic
Arithmetic for Real Data Types and Support for Matlab/Simulink based Rapid-FPGA
-Prototyping."
Laboratoire de l'Informatique du Parallelisme,
(CNRS, ENSL, INRIA), France
Title: "Some
Modular Adders and Multipliers for Field Programmable Gate Arrays."
Ngee Ann Polytechnic DSP Technology Center,
Singapore
University of Applied Science, Darmstadt, Germany
University of Aberdeen, Scotland
Title: "A
Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software
Defined Radio."
University of Leipzig, Germany
Title: "A
Novel Design Technology for Next Generation Ubiquitous Computing Architectures."
Inha University, Yong-Hyun Dong, Incheon, Korea
Title: "Evolutionary
Reconfigurable Architecture for Robust Face Recognition."
University of Paderborn, Germany
Wallmedien AG, Paderborn, Germany
Title: "A
Reconfigurable Message Oriented Middleware Architecture."
University of Ferrara, Italy
Ecole Polytechnique Fédérale de Lausanne,
Switzerland
Title: "Performing
DNA comparison on a bio-inspired tissue of FPGAs."
18.00 - 18.10: Closing Remarks