23 April 2002, 17:42:34 CDT
A meeting has been tentatively set for this Thursday, 25 April at 17:00 in room 117. Let me know if you can't make it.
21 March 2002, 10:01:22 CST
Linked Verilog description of a dynamically scheduled processor to this page. The code will be difficult for those who have not taken EE 4720.
Meeting scheduled for Friday, 22 March 2002 (tomorrow). We will discuss early progress on the projects and refine project ideas.
12 March 2002, 13:48:47 CST
A meeting has been tentatively set for Friday, 15 April, 2002 at 16:00 in room 117. If you can't make it let me know as soon as possible.
Using these guidelines prepare a project proposal for the meeting. We will discuss projects at the meeting and may cover some Verilog material. The overlapping material in EE 3755 has been finished. The remaining topics to be covered are listed here. Please finish studying them by the end of Spring Break.
22 February 2002, 11:23:11 CST
Coverage of Verilog will resume in EE 3755 starting today. Please resume attending starting today.
22 February 2002, 9:08:37 CST
There is no meeting on Friday, 22 February. The previous what's new entry was a mistake (now corrected).
14 February 2002, 15:23:57 CST
Meeting set for 15:40 on
22 15 February in room 117 EE Building.
14 February 2002, 12:27:13 CST
So far 7 of 10 have responded to the E-mail about the meeting time. Six can make a 15:40 (rather than 15:30) meeting tomorrow, one can make it at 16:35, and three have not responded. The meeting is tentatively set for 15:40 in room 117 EE building, though the time might be delayed to 16:00 or 16:30. If those times are not appropriate let me know.
13 February 2002, 16:19:45 CST
An independent study meeting is tentatively set for Friday, 15 or 22 February 2002 at 15:30. Please let me know if you can or cannot make either day. We will meet on the earlier day if everyone responds quickly.
For about the next three lectures integer arithmetic will be covered in EE 3755. During that time please study the following sets of notes: Basics of Procedural Code, Data Types, Operators (most material in this set is also covered in EE 3755, the exception begin reduction operators), and Gate, Wire, and Module Delays (some material covered in EE 3755). An easy homework assignment will be given based on this reading.
Some time this week a course schedule will be posted here.
1 February 2002, 17:27:33 CST
Added instructions to obtain and set up an indpendent study class account, see procedures. Please report any problems immediately. When you get the account working, solve EE 3755 homework 1.
1 February 2002, 14:53:52 CST
Independent study students will need to obtain a class account manually using these easy steps: (1) Get a Sun Account Application from Saied Andalib's office in room 150. (2) Fill out the form, use "Verilog Independent Study" for the purpose of the account. (3) Bring the form to me (Dr. Koppelman) for my signature. (4) Return the form to Saied.
If you already have a Sun account you can use that instead, either way the account will have to be set up for the software.
Instructions for setting up the account will be posted here soon.
If you have not already done so, E-mail me your E-mail address.
16 January 2002, 15:25:20 CST
Updated Web pages for Spring 2002 independent study Verilog course.
Spring 2001 what's new.
|David M. Koppelman - firstname.lastname@example.org||Modified 25 Apr 2002 16:18 (2118 UTC)|