EE 4702-X - What's New

23 May 2001, 10:11:24 CDT
Removed grades and added a link to a Fall 2001 EE 4702-1 course, on synthesis.

15 May 2001, 14:04:35 CDT
Linked final exam solution and related Verilog code. to assignments and exams page.

Note: The behavior of an if statement was described incorrectly in class. If the if condition is unknown or high impedance the else condition does execute.

14 May 2001, 18:52:37 CDT
Course Grades Ready
@( posedge nerve ) click here.
A solution to the final will be posted in a few days.
Everyone have a good summer!

14 May 2001, 18:21:04 CDT
Graded Homework 5 E-mailed to class accounts and solution linked to assignments and exams page. (A solution to the final will be posted in a few days.) Grades should be ready within an hour.

14 May 2001, 15:13:47 CDT
Grades should be available by the early evening.

13 May 2001, 17:52:43 CDT
Grading Update: E-mailed Homework 4 grades. Homework 5 grades will be sent tomorrow. Course grades will be available tomorrow unless it's tough to choose the breakpoints, in which case they will be ready early Tuesday. (That's not a bad thing because the longer I think about grade cutoffs, the higher they get. :-) ) The next grading update will be tomorrow early afternoon.

12 May 2001, 18:01:44 CDT
Nothing new today. The next grading update will be Sunday, late afternoon. By then some homeworks will be graded. Course grades will not be decided before Monday.

10 May 2001, 17:34:04 CDT
Final Exam Grades Ready
The range was [22,97], the average was 56.8. Prepare yourself and click here.

The homework and course grades will be available next week or possibly over the weekend. The next grading update will be posted Saturday afternoon, or possibly Friday (with the results of homework grading).

10 May 2001, 13:00:54 CDT
Problems 1,2, and 3 graded. Final exam grades will be available in the late afternoon.

9 May 2001, 17:37:18 CDT
Problems 1 and 2 graded. Exam grades may be ready tomorrow late afternoon. The next grading update will be tomorrow, around noon.

9 May 2001, 10:20:04 CDT
Linked final exam to assignments and exams page. Material will be graded in this order: final exam, hw 4, hw 5, course grade. Homework 3 grades will be E-mailed soon, check your class account. A grading update will be posted this evening.

4 May 2001, 16:27:28 CDT
Linked midterm exam solution and related Verilog code to assignments and exams page.

4 May 2001, 13:09:36 CDT
Illustrations have been added to problem 3 in the Spring 2000 final exam solution and related Verilog code.

4 May 2001, 10:23:30 CDT
Linked homework 4 solution to assignments and exams page.

4 May 2001, 9:50:39 CDT
Linked Final Exam Review to lectures page. Later today illustrations will be added to the solution of the 2000 final exam solution.

3 May 2001, 13:18:46 CDT
Linked Set 200, Elements of VHDL and VHDL examples: Binary full adder (BFA)., Adders some using BFA., Population counter., and Calculator. to lectures page.

2 May 2001, 10:42:24 CDT
Linked Set 120, Form 3, pops.v (population count), and am.v (associative memory) to lectures page.

For hints on Homework 5 look at the variations on the population count module presented in class.

1 May 2001, 13:16:43 CDT
Job Opportunity: Drs. Rai, Trahan, and Vaidyanathan are looking for an undergraduate student to do Verilog or VHDL coding over the summer. See the job announcement for details. [Note: Link to job ad removed around 15 May 2001, 14:07:12 CDT].

1 May 2001, 13:08:29 CDT
<blush>Homework 5 was mistakenly copied this morning.</blush> It will be copied again the night of Wednesday, 2 May.

26 April 2001, 13:44:20 CDT
It turns out the bsearch module in Homework 5 is synthesizable, but not in a way appropriate for problems 1 and 2. In those problems, the synthesized module must perform no more than one iteration of the forever loop per cycle. In problem 3 the synthesized module must perform no more than two iterations per clock cycle. The Homework 5 handout has been updated with this information.

25 April 2001, 10:35:56 CDT
Assigned the last homework, Homework 5, due Wednesday, 2 May 2001.

23 April 2001, 19:18:13 CDT
Re-wrote synthesis script that might avoid problems. (Synthesis script would synthesize but would not compile synthesized modules.) The new script is called, use it the same way as syn.tcl. Those using Emacs since 19:15 today should exit and restart it to get it to use the new script. Hint: Beware the inferred parallel case. If wildcards are used in case items (e.g., 4'bxxx) the synthesis program might incorrectly infer the parallel case. A workaround is to add extra code in the case item's statement to double check for the correct expression.

20 April 2001, 18:38:22 CDT
Added an improved testbench to the template for Homework 4.. The testbench provides more information and will pass some code that would previously fail.

On some accounts the synthesis script gives an error: error reading output from command: interrupted system call Until a fix is available, use the following workaround: Suppose the error occurs when synthesizing hw04sol.v. Compile the synthesized design, should be in file hw04sol_1.v, as you would any other Verilog file. (In Emacs, by loading it into a buffer and pressing F9.) After that the synthesized design can be simulated.

18 April 2001, 18:30:07 CDT
Added questions on whether it's okay to use the Homework 3 solution in Homework 4 (it is), and about problems with Modelsim and Leonardo to the FAQ page.

18 April 2001, 11:28:18 CDT
The deadline for Homework 4 has been extended to Monday at 23:59 CDT. The files will be copied on Tuesday at 00:30.

The Homework 3 solution will now reject entries such as 90.

16 April 2001, 18:37:45 CDT
Made improvements to the testbench in the template for Homework 4. It should catch more errors and gives more informative "Wrong display" messages.

11 April 2001, 16:03:39 CDT
Linked Set 090, synthesis overview, Set 100, Form 1, Set 110, Form 2, and calculator example in unsynthesizable, and synthesizable, versions to the lectures page. An improved testbench may not be posted until Monday.

10 April 2001, 19:29:05 CDT
Linked a Homework 3 solution to assignments and exams page. This can be used to solve Homework 4. An improved Homework 4 testbench will be posted tomorrow.

10 April 2001, 16:35:12 CDT
There was a problem with the testbench included in the template for Homework 4. The testbench would report everything was okay but would not actually do any tests. The posted code is now correct, if you've already copied it then change the line that looks like:

      input [159:0] cmd;
      input [799:0] cmd;
To verify that the testbench is working, trace the key_code input to your module (using the wave window).

9 April 2001, 19:56:18 CDT
Homework 4 assigned, due 20 April 2001.

9 April 2001, 9:43:22 CDT
Deadline for late submissions of Homework 3 is today (Monday) at 17:00 (5pm).

20 March 2001, 8:24:45 CST
Due date for Homework 3 set to Wednesday, 4 April 2001 23:59 CDT.

18 March 2001, 13:22:15 CST
Midterm Exam Grades Ready. The average is 54.2, the range [93,14], the standard deviation is 19.7. Get ready, remember that the test was difficult for everyone, and click here.

17 March 2001, 16:04:33 CST
Grading Update: The midterm exam grades will be posted tomorrow in the early afternoon. (Don't forget to reload.)

16 March 2001, 18:12:04 CST
Grading update: Problems 1 and 2 graded. Getting the exam back on Monday is within the realm of possibility.

16 March 2001, 9:55:45 CST
Linked Midterm Exam to assignments and exams page. Grading updates and solutions will be posted later.

15 March 2001, 12:27:07 CST
For the oven in Homework 3, the number of seconds must be in [0,59]. If the user enters something like 90 START the oven should beep. The user can enter another digit or press reset to start over.

14 March 2001, 9:51:48 CST
Reminder: The midterm exam is this Friday, 16 March 2001 at 8:40 (come early if possible). The exam is closed book, also excluded are communication devices. Bring any amount of materials as long as they can be carried 100 meters without resting.

12 March 2001, 10:14:50 CST
Linked Set 080, functions and tasks, to lectures page. Also linked bad function example and calculator example to lectures.

11 March 2001, 17:54:08 CST
Linked Homework 3 to assignments and exams page. A due date has not been determined, but it will be after the exam. However solving the homework will make good practice for the exam. See the calculator example, to be presented in class tomorrow, for ideas on solving the homeowrk.

9 March 2001, 12:04:38 CST
Homework 2 graded, graded submission E-mailed to class account.
Solution to Homework 2 linked to assignments and exams page. Includes grading code.

8 March 2001, 13:47:56 CST
Homework 1 graded. Graded submission E-mailed to class account.

5 March 2001, 16:23:05 CST
Linked Set 070,include, define, etc., to lectures page. Also updated Set 060.

2 March 2001, 9:42:18 CST
Midterm Exam Date Set: Friday, 16 March 2001. The exam will be held in class and will be closed book but open notes. Additional details posted later.

19 February 2001, 12:27:00 CST
Linked solution to Homework 1 to assignments and exams page.

16 February 2001, 12:43:56 CST
Linked Set 060, procedural delays and related statements, to lectures page.

15 February 2001, 17:34:28 CST
Homework 2 assigned, due 22 February, one second before midnight.

13 February 2001, 9:50:25 CST
The TA-bot copied assignments about 00:01 this morning. Check your class account E-mail for a confirmation message.

9 February 2001, 15:37:20 CST
Homework 1 hint: The inputs and outputs of modules priority_encoder_1_es, priority_encoder_1_is, and priority_encoder_1_b are each one bit. That is, grant, found_out, request, and found_in are each one bit. Read Homework 1 Problem 2 carefully, some of what it described applies to Homework 2.

9 February 2001, 10:14:01 CST
The TA-bot will copy solutions to Homework 1 from class accounts no earlier than 23:59:59 Monday 12 February. Assignments should be complete and properly named by midnight Monday. If the assignments are not properly named the TA-bot will try guessing a name, it's good but not perfect.

7 February 2001, 9:57:01 CST
Added material on case statement to Set 040,Conditional, Looping, etc and linked Set 050, Delays to lectures page.

6 February 2001, 10:39:13 CST
Emacs, Modelsim (the Verilog [and VHDL] simulator), and Leonardo (the synthesis program) can now be started from the CDE program panel in class accounts. Emacs is started using the overflowing kitchen sink icon. The other programs are started by the subpanel above Emacs, made visible by clicking the triangle above the Emacs icon.

6 February 2001, 7:57:00 CST
Slightly clarified the description of the priority encoder in problem 2 of Homework 1, Due 12 February.

5 February 2001, 9:43:59 CST
Linked population modules to lectures page and added disable to Set 040,Conditional and Looping .

4 February 2001, 20:13:22 CST
Homework 1 assigned, due 12 February 2001.

Instructions (procedures) for using the simulator and text editor updated for this semester. Links on the references page updated.

2 February 2001, 16:19:47 CST
Linked Conditional and Looping notes to lectures page.
The procedures for using the text editor and simulation software linked to the class web page are from last year, they will be updated over the weekend.

1 February 2001, 14:31:46 CST
Linked Operators notes to lectures page.

26 January 2001, 11:52:54 CST
Linked Behavioral Basics and Variables, Data Types, Constants to lectures page. Minor changes made since being shown in class, including references to textbook and the Verilog Language Reference Manual (LRM). See references.

24 January 2001, 10:04:13 CST
Linked binary full adder example to lectures page.

19 January 2001, 10:25:26 CST
Linked XOR gate example to lectures page.

17 January 2001, 10:21:58 CST
Linked Set 1 of lecture slides to lectures page.

8 December 2000, 17:06:46 CST
Updated Web pages for Spring 2001 semester.

Spring 2000
Spring 2000 what's new.

ECE Home Page Course Home Page
David M. Koppelman -
Modified 23 May 2001 10:12 (1512 UTC)