EE 4755, Digital Design Using HDLs


When / Where / Details

Fall 2017: MWF 9:30-10:20 CT Room 225 Tureaud Hall
Fall 2017 Syllabus

Current Lectures

Lecture slides and examples used in class.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

Assignments and Exams

Includes solutions.
Screenshot of design.
RSS Feed What's New
22 November 2017, 10:44:21 CST
Fixed minor problems discovered during class in the Simple Model slides and the preliminary Homework 6 solution.

22 November 2017, 9:18:46 CST
Linked some Simple Model slides and the Event Queue slides to the lectures page. Also linked a preliminary Homework 6 solution to the assignments and exams page.

19 November 2017, 15:45:25 CST
Homework 7 assigned, due 29 November 2017. Start early.

What Was New
33 more items starting 13 November 2017, 9:12:41 CST.


ECE Home Page
David M. Koppelman - koppel@ece.lsu.edu
Modified 22 Nov 2017 10:45 (1645 UTC)