EE 3060 - Independent Study Topics
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In the Spring 2002 semester the Verilog course is being offered as an
independent study class. Please study the topics listed below
starting 12 March 2002 and finishing by 8 April 2002.
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Self-Study Objectives
Tasks and Functions (l080)
Define your own tasks and functions.
Understand why functions are more synthesizable than tasks.
Delayed Assignment (l060)
Understand how delayed assignment work.
Use of zero delay for synthesizable clocked logic.
Use of non-zero delay in testbench.
Advanced Procedural Topics (l040)
Use fork/join to replace several always blocks.
Use fork/join to watch several variables.
Use of disable within loops.
Use of case_full and case_parallel (check names).
Compiler Directives, Parameters, Named Ports, etc. (l070)
Use hierarchical referencing in a testbench to peek inside a tested module.
Use defines to ease changes, for example, vector sizes.
Use of parameters in module instantiation.
