This project, led by LSU and based also at UNO and ULL, is developing new techniques to perform early detection of abnormal performance in airplanes and to reconfigure the flight control systems accordingly. It is expected that the results will enhance the safety of the commercial fleet.

An analytic approach is taken to modeling wideband OFDM channels, which is in contrast to the existing experimental approach in modeling wideband and ultra-wideband wireless channels.

Computer Vision, the science of recognizing patterns in visual imagery, has a wide range of applications. This talk presents an overview of projects at the Exploratory Computer Vision Group in the IBM Watson Research Center. I will briefly describe our work in automatic object recognition (VeggieVision), automatic video indexing for broadcast (VideoVista), and audio-visual speech recognition. The focus of the talk will be around Biometrics and Video Surveillance.

A vertical comb-drive actuator is an advanced torsional electrostatic MEMS actuator. It has higher force density with extended effective capacitance area and has wider moving range due to pull-in-free characteristic in comparison with a conventional parallel-plate type electrostatic actuator. This talk will focus on the application of the vertical comb-drive actuators to optical and RF areas including a low-voltage scanning micromirror array for a wavelength selective switch (WSS), a two-axis tilt micromirror for three-dimensional optical crossconnect (OXC), a flat-and-fast MEMS scanner, and a high-tuning-ratio tunable capacitor. This talk will also cover the hybrid analysis method for the vertical comb-drive actuators, which combines the two-dimensional finite element method and the analytic method.

My research has explored the interactions between architecture design and lower level design in order to facilitate both design and verification processes. In the contemporary design process, a problem with the widely used flip-flop insertion method for interconnects is that it is not aware of the microarchitecture constraints. Therefore I have used a statistical method to quantify each interconnects impact on microarchitecture, which was later used as the constraints in the floor planning process. In this manner, I have achieved a design with optimal balance among architecture performance, interconnects latency, and the area of the layout. In the verification process, test vectors generated from the architecture/system verification have been used as inputs for RTL simulations for debugging. However the test vectors generated were not optimized and thus resulted in unreasonable simulation time. To optimize the test vectors generation, I have proposed both a single heuristic algorithm and a multiple simultaneous heuristics algorithm. Both algorithms have been proven to be efficient in discovering different types of bugs for Cray X1 and Stanford DASH cache coherence protocols. I have also proposed a novel memory structure with flexible sequential and random access modes for embedded systems, and conducted research in exploiting the prefetching effect of speculative execution in a multithreaded architecture.

Load latency introduces one of the most difficult performance issues in modern microprocessors. It takes hundreds of cycles to load data from memory. Even when the data is present in caches, the inherent delay may still prevent load dependents from issuing flawlessly. In this talk, I will present a new mechanism to improve load performance. We observe that store-load and load-load dependences have high correlations through the encoding bits of the instruction code. We introduce a novel addressing scheme for loads/stores to avoid any address calculation. The new addressing scheme allows data accessing early in the pipeline to achieve zero-cycle loads. Performance evaluations based on an Alpha 21264-like pipeline using SPEC2000 benchmarks have showed significant performance improvement.

In addition, I will present a trace-driven simulation method to study memory behaviors of emerging multithreaded applications running on multiprocessors with shared caches. We observe opposite memory reference behaviors, constructive or disruptive, could result from parallelization. The proposed method can provide memory access locality information to guide program parallelization.

A detailed investigation focused upon evaluating the effects dimensional nanoscaling of silicon features on the optical and electronic properties is presented. The feature dimensions in this study ranged from ≅200nm down to ≅10nm. This range represents the transition region from material bulk properties towards the onset of quantization. These structures were fabricated on silicon-on-insulator using interferometric lithography, reactive-ion-etching and thermal oxidation methods. In order to investigate the optical and electronic properties, the nanostructures were configured in a two terminal metal-semiconductor-metal test device arrangement. The metal-semiconductor-metal configuration was chosen for this study due to its practicality in photonic and electronic parameter characterization and the ease of device fabrication. Characterization methods included steady-state DC measurements and transient time response measurements using a modified version of the Haynes-Shockley experiment for evaluating the carrier mobility as a function of feature size. Results show that the total carrier drift-diffusion dependent conduction for same biasing conditions increased as the feature dimension was reduced from ≅200nm to ≅10nm. The transient time response measurements show that the low field electron mobility can be increased in the best case at room temperature from ≅1000 cm²/V-s to ≅4000 cm²/V-s as the cross-sectional area becomes narrower due to confinement effects. Theoretical models for optical coupling and electronic transport properties are provided to give physical insight at these small scales.

Recent years have seen a proliferation of complex System-on-Chips (SoCs) that are composed of multiple processor cores and other Intellectual Property (IP) cores. These cores are connected by the on-chip communication architecture (OCA).

In this talk, I will introduce a retargetable simulation framework where SoC designs, including the OCAs, can be constructed easily and evaluated efficiently and faithfully. The modeling and simulation platform is based on an existing formal concurrency model, the Operation State Machine (OSM). The OCA models are constructed faithfully by explicitly modeling both the operation concurrency and the microarchitecture concurrency. Coupled with existing Processor Element (PE) models, this framework is capable of synthesizing a multiprocessor cycle-accurate SoC simulator from a system-level description. The case studies aim to examine and evaluate this framework. The targeted architectures include a router-based packet switching on-chip communication network and an industry-standard on-chip bus architecture. Experimental results show that this framework can significantly reduce the design turn around time and improve design reuse in the early stages of SoC design.

Xinping Zhu is currently a Ph.D. candidate in Electrical Engineering at Princeton University. He received his B.S.E. degree in Automation from Tsinghua University, Beijing, in 1999. His research focuses on developing modeling and simulation tools for advanced multiprocessing general purpose and embedded processors, with emphasis on the on-chip communication architectures.

Even as the high performance computing community approaches 100 Teraflops Linpack performance, challenges to supercomputer hardware and software design may impede further progress and limit scalability and performance to cost. The impact of latency, overhead, contention, and starvation are already limiting delivered efficiencies on the world's largest machines to a few percent for some critical applications. The consequence of these factors may be reduced impact of supercomputing on science, technology, industry, commerce, national security, and society even as its capability approaches important new levels. While commodity microprocessor and DRAM based clusters and MPPs have dramatically advanced the scale of high end computing over the last decade, reliance on devices expressly designed for consumer electronics and commercial enterprise computing may impose severe limitations on future expansion of those same capabilities. Fortunately, exploration of innovations in parallel architecture and methods has revealed advanced but practical strategies that aggressively attack these sources of performance degradation and may deliver future systems that efficiently perform a wide range of challenging algorithms across the trans-Petaflops performance regime. This presentation will diagnose the causes of current inefficiencies on conventional systems and describe the seminal innovations that are likely to circumvent their deficiencies. An exemplar of such advanced strategies is the Gilgamesh MIND architecture, a multicore processor-in-memory scalable computing component supporting a lightweight split-transaction processing model with message-driven computation. The MIND architecture is being developed to explore the far reaches of possible computing capability through modeling and simulation and as a possible approach to implementing future cost-effective supercomputers in the pan-Petaflops performance regime.

Image quality assessment research aims to provide objective measures that can automatically predict perceived image quality. An image quality measure can play an important role in a wide variety of image processing applications, for system benchmarking, quality monitoring, and algorithm optimization purposes. This talk summarizes a number of our recent works on full-reference (FR), reduced-reference (RR) and no-reference (NR) image quality assessment. Specifically, we introduce an adaptive linear system framework for FR image distortion analysis. The major difference from standard linear analysis systems (such as Fourier and wavelet systems) is that the basic components are not fixed, but adaptively computed from the image signals being analyzed. For RR quality assessment, we propose a wavelet domain information distance measure based on a natural image statistic model. This gives an efficient RR method that works effectively for a wide range of distortion types. Finally, we show that complex wavelet transforms can be used to characterize the local phase structural regularity of natural images. This provides a novel theory that may explain how an image is perceived to be sharp or blurred, and implies a new NR algorithm for the detection and correction of space-variant blur.

Simulations are playing an increasingly important role in science and engineering and are rapidly becoming critical research modalities. Adaptive and interactive simulations can yield highly advantageous cost/accuracy ratios and can enable accurate solutions to realistic models of complex physical phenomenon. However, the phenomena being modeled by these simulations and their implementations are inherently dynamic and heterogeneous, and their large scale implementation presents many challenges. In this talk I will first describe a computational engine that enables efficient and scalable implementations of these applications. Specifically, I will address dynamic data-management, adaptive load-balancing, and interactive monitoring and control. I will then outline the challenges presented by emerging Grid-based simulations that combine computations, experiments, observations, and real-time data, and will introduce our ongoing research efforts to address these challenges.