• Title: Digital Integrated Circuits
• Catalog Description: Prereq.: EE 3220, 3221, and 3232. 2 hrs. lecture; 2 hrs. lab. ABET category: 2 hrs. design; 1 hr. engineering science. Analysis and design of digital integrated circuit logic gates in bipolar and MOS technology; semiconductor memories and their operations.
  
• Instructor: Dr. DooYoung Hah
  
• Lecture: MW 8:40-9:30, 225 TUREAUD HALL
  
• Lab: EE 252
  • Session 1: T 8:40-10:30, instructor - Dr. DooYoung Hah
  • Session 2: T 3:40-5:30, instructor - Mr. Siva Yellampalli
• Office hour: MW 9:40-11:40 AM, T 10:40-11:40 AM
  
• Textbook: Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, D. A. Hodges, H. G. Jackson and R. A. Saleh, McGraw-Hill, 3rd Edition, 2003.
  
• Exam Schedule
  • Test1: Feb. 12, Mon., in-lecture
  • Test2: Mar. 26, Mon., in-lecture
  • Final: May 7, Mon., 3-5 pm

    Notices and Announcements

• Final exam results and grades have been posted in front of EE229. NEW!!
• Solution to the test2 (3/26)
• Test2, 3/26, in-class
  • You may prepare a double-sided formula sheet, 3" x 5" in size.
• Lab schedule change (3/12)
  • Original: Project - 4/10, Lab#9 - 4/17
  • Revised: Lab#9 - 4/10, Project - 4/17
• Solution to the test1 (2/15)
• Test1, 2/12, in-class
  • Closed-book, closed-note
  • Only calculators with simple functions are allowed.
• Course syllabus (lecture & lab) (1/17)
• There will be no lab during the first week. (1/16)
• Errata of the text book (Under Student Resource)
• Welcome to the course website of EE4250, spring 2007.

    Course Materials

• 2. BJT inverters and TTL
  
• 3. MOS transistors (in one file)
  
  • Part I
    
  • Part II
    
  • Part III
    
  • Part IV
    
• 4. MOS Inverter Circuits
  
• 5. Static MOS Gate Circuits (in one file)
  
  • Part I
    
  • Part II
    
  • Part III
    
• 6. High-Speed CMOS Logic Design (in one file)
  
  • Part I
    
  • Part II
    
• 7. Transfer Gate and Dynamic Logic Design NEW
  
  • Part I
    
  • Part II
    

    Solutions to the Home Assignments

• Home Assignment #5 (revised on 4/24)
  
• Home Assignment #4 (3/26)
  
• Home Assignment #3 (revised on 3/19)
• Home Assignment #2 (3/7)
  
• Home Assignment #1 (2/12)
  

    Datasheets for the Components Used in the Lab

• 2N2222A: Philips NPN switching transistor
  
• 74LS00: Motorola Quad 2-input NAND gate
  
• CD4001: National Semiconductor Quad 2-input NOR gate
  
• BS170: Philips Semiconductors BS170 NMOS
  
• BS250: Philips Semiconductors BS250 PMOS
  

    A Little Help for the SPICE Simulation

• Try the simulation example that CADENCE PSPICE offers.
  • Run the CAPTURE CIS under CADENCE PSD 15.1 from the START menu.
  • Select MANUAL under the HELP pull-down menu.
  • Find and open /PSPICE/PSPICE User's Guide/2.Simulation Examples.
  • Follow the instructions.