NICE,
France
Tuesday, April 22, 2003
The 10th Reconfigurable Architectures Workshop
(RAW 2003)
will be held at the
Nice
Acropolis Convention Center,
Nice,
France, on Tuesday, April 22, 2003. RAW 2003 is associated with the 17th Annual
International
Parallel & Distributed Processing Symposium (IPDPS 2003)
and is
sponsored by the
IEEE Computers
Society's
Technical
Committee on Parallel Processing. RAW 2003 is one of the major meetings
for researchers to present ideas, results, and on-going research on both
theoretical and practical advances in Reconfigurable Computing.
Main
Focus of the Workshop:
Run-Time
& Dynamic Reconfiguration: Architectures, Algorithms, Technologies
Run-Time and Dynamic Reconfiguration are
characterized by the ability of underlying hardware architectures or devices
to rapidly alter (on the fly) the functionalities of its components
and the interconnection between them to suit the problem. Key to this ability
is reconfiguration handling and speed. Though theoretical models and algorithms
for them have established reconfiguration as a very powerful computing
paradigm, practical considerations make these models difficult to realize.
On the other hand, commercially available devices (such as FPGAs and new
coarse-grain FPFAs) appear to have more room for exploiting run-time reconfiguration
(RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration,
and practical considerations, including architectures, technologies and
tools supporting RTR is essential to fully reveal and exploit the possibilities
created by this powerful computing paradigm. RAW 2003 aims to provide a
forum for creative and productive interaction between all these disciplines.
Topics
of Interest:
Authors are invited to submit manuscripts
of original unpublished research in all areas of dynamic and run-time reconfiguration
(foundations, algorithms, hardware architectures, devices, systems-on-chip
(SoC), technologies, software tools, and applications). The topics
of interest include, but are not limited to:
Models & Architectures
Theoretical Models (RMesh, etc.)
RTR Models and Systems
RTR Hardware Architectures
Optical Interconnect Models
Simulation and Prototyping
Bounds and Complexity Issues
|
Algorithms & Applications
Algorithmic Techniques
Mapping Parallel Algorithms
Distributed Systems & Networks
Fault Tolerance Issues
Wireless and Mobile Systems
Automotive Applications, etc.
|
Technologies & Tools
Configurable Systems-on-Chip
Energy Efficiency Issues
Devices and Circuits
Reconfiguration Techniques
High Level Design Methods
System support
|
Authors' Resources:
Click
here
Important
Dates:
-
Manuscript due
November 4, 2002
-
Notification of acceptance/rejection
December 5, 20022002
-
Final version due
Organization
:
Workshop Chair:
Serge Vernalde, IMEC, Belgium
vernalde@imec.be
Steering Chair:
Viktor K. Prasanna, University of Southern California, USA
prasanna@ganges.usc.edu
Program Chair:
Juergen Becker, Universitaet Karlsruhe (TH), Germany
becker@itiv.uni-karlsruhe.de
Publicity Chair:
Ramachandran Vaidyanathan, Louisiana State University, USA
vaidy@ece.lsu.edu
Program
Committee:
-
Jeffrey Arnold, Adaptive Silicon, Inc., USA
-
Juergen Becker, Universitaet Karlsruhe (TH),
Germany
-
Don Bouldin, University of Tennessee, USA
-
Gordon Brebner, University of Edinburgh, UK
-
Klaus Buchenrieder, Infineon Technologies,
Germany
-
Thomas Buechner, IBM, Germany
-
Oliver Diessel, University of New South Wales,
Australia
-
Carl Ebeling, University of Washington, USA
-
Hossam ElGindy, University of New South Wales,
Australia
-
Manfred Glesner, Darmstadt University of Technology,
Germany
-
Steve Guccione, Quicksilver Technology, USA
-
Herbert Gruenbacher, Carinthia Tech. Institute,
Austria
-
Reiner Hartenstein, University of Kaiserslautern,
Germany
-
Brad Hutchings, Brigham Young University,
USA
-
Mark Jones, Virginia Tech, USA
-
Peter Jung, Gerhard Mercator University, Duisburg,
Germany
-
Mohammed A. S. Khalid,
Cadence Design Systems, USA
-
Hyoung-Joong Kim,
Kangwon National University, Korea
-
Fabrice Kordon, Université Pierre &
Marie Curie, Paris, France
-
Rainer Kress, Infineon Technologies, Germany
-
Markus Kuehl, Forschungszentrum Informatik
(FZI), Karlsruhe, Germany
-
Rudy Lauwereins, IMEC, Leuven, Belgium
-
Philip Leong, Chinese University of Hong Kong,
China
-
Marnane Liam, University College, Ireland
-
Rong Lin, State University of New York, Geneseo,
USA
-
Wayne Luk, Imperial College, UK
-
Juergen Luka, DaimlerChrysler AG, Germany
-
Patrick Lysaght, Xilinx, USA
-
Malgorzata Marek-Sadowska, University of California,
Santa Barbara, USA
-
John McHenry, National Security Agency, USA
-
Alessandro Mei, University Rome "La Sapienza",
Italy
-
Martin Middendorf, Katholische Universität
Eichstätt, Germany
-
George Milne, University of Western Australia,
Australia
-
Toshiaki Miyazaki, NTT Network Innovation
Labs., Japan
-
Amar Mukherjee, University of Central Florida,
USA
-
Dietmar Mueller, Technische Universitaet Chemnitz,
Germany
-
Koji Nakano, Japan Advanced Inst. of Science
& Tech., Japan
-
Bernard Pottier, Université de Bretagne
Occidentale, France
-
Michel Renovell, LIRMM, France
-
Peter Roth, IBM, Germany
-
Sakir Sezer, Queen's University, N. Ireland,
U.K.
-
Hartmut Schmeck, Universität Karlsruhe
(TH), Germany
-
Juergen Teich, University of Paderborn, Germany
-
Lionel Torres, LIRMM, Montpellier, France
-
Jerry L. Trahan, Louisiana State University,
USA
-
Ramachandran Vaidyanathan, Louisiana State
University, USA
-
Serge Vernalde, IMEC, Belgium
-
Martin Vorbach, PACT Informationstechnologie,
Germany
-
Norbert Wehn, University of Kaiserslautern,
Germany
-
Peixin Zhong, Lucent Technologies, USA
RAW
2003 Home
http://www.ece.lsu.edu/vaidy/raw03/