NICE, France
Tuesday, April 22, 2003

The 10th Reconfigurable Architectures Workshop (RAW 2003) will be held at the Nice Acropolis Convention Center, Nice, France, on Tuesday, April 22, 2003.  RAW 2003 is associated with the 17th Annual International Parallel & Distributed Processing Symposium (IPDPS 2003) and is sponsored by the IEEE  Computers Society's Technical Committee on Parallel Processing. RAW 2003 is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

Main Focus of the Workshop:

Run-Time & Dynamic Reconfiguration: Architectures, Algorithms, Technologies

Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly  alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-grain FPFAs) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2003 aims to provide a forum for creative and productive interaction between all these disciplines.

Topics of Interest:

Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and  applications). The topics of interest include, but are not limited to:

Models & Architectures
  • Theoretical Models (RMesh, etc.)
  • RTR Models and Systems 
  • RTR Hardware Architectures 
  • Optical Interconnect Models 
  • Simulation and Prototyping 
  • Bounds and Complexity Issues 
  • Algorithms & Applications
  • Algorithmic Techniques 
  • Mapping Parallel Algorithms 
  • Distributed Systems & Networks 
  • Fault Tolerance Issues 
  • Wireless and Mobile Systems 
  • Automotive Applications, etc. 
  • Technologies & Tools
  • Configurable Systems-on-Chip 
  • Energy Efficiency Issues 
  • Devices and Circuits 
  • Reconfiguration Techniques 
  • High Level Design Methods 
  • System support 


    Authors' Resources:     Click here

    Important Dates:

    Organization :

    Workshop Chair:    Serge Vernalde, IMEC, Belgium
    Steering Chair:       Viktor K. Prasanna, University of Southern California, USA
    Program Chair:      Juergen Becker, Universitaet Karlsruhe (TH), Germany
    Publicity Chair:      Ramachandran Vaidyanathan, Louisiana State University, USA

    Program Committee:

    RAW 2003 Home