EE 4755, Digital Design Using HDLsWhen / Where / Details
Current LecturesLecture slides and examples used in class.
Computer StatusThe current status of the computers in the
back of Room 2241 P.F. Taylor Hall. Updated every 10 minutes.
ProceduresInstructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
ReferencesSoftware manuals and information on Verilog.
Study GuideAdditional material on Verilog inference and synthesis.
GradesWhat's PopularThe most accessed Web pages for this course over the
past three days.
Assignments and ExamsIncludes solutions. |
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David M. Koppelman - koppel@ece.lsu.edu | Modified 14 Dec 2021 12:03 (1803 UTC) |
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