EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2025: MWF 11:30-12:20 CT 1206 Taylor Hall
Fall 2025 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

What's Popular

The most accessed Web pages for this course over the past three days.

Assignments and Exams

Includes solutions.
 Screenshot of design.
RSS Feed What's New
3 December 2025, 13:16:55 CST
Late submissions of Homework 5 will be copied, Friday morning, 5 December 2025.

For Friday's class please look over the 2024 final exam.

29 November 2025, 15:56:49 CST
Linked the Homework 4 solution code to the assignments and exams page. Graded Homework 3 and 4 submissions will be returned tomorrow.

21 November 2025, 19:11:19 CST
Homework 5 assigned, due Sunday night, 30 November 2025. Late submissions will be accepted.

What Was New
24 more items starting 11 November 2025, 18:26:28 CST.

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