EE 4755, Digital Design Using HDLs
When / Where / Details
| Fall 2025:
MWF 11:30-12:20 CT
1206 Taylor Hall Fall 2025 Syllabus |
Current Lectures
Lecture slides and examples used in class.
Computer Status
The current status of the computers in
Room 2241 P.F. Taylor Hall. Updated every 10 minutes.
Procedures
Instructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
References
Software manuals and information on Verilog.
Study Guide
Additional material on Verilog inference and synthesis.
Grades
What's Popular
The most accessed Web pages for this course over the
past three days.
Assignments and Exams
Includes solutions.
What's NewHomework 1 assigned, due Wednesday, 17 September 2025. This is an easy assignment. Problem 1 is collected by the TA-bot, Problem 2 should be handed in on paper or E-mailed.
5 September 2025, 15:55:34 CDT
25 August 2025, 15:49:33 CDT
What Was New |