EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2025: MWF 11:30-12:20 CT 1206 Taylor Hall
Fall 2025 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

What's Popular

The most accessed Web pages for this course over the past three days.

2 November 2025, 13:06:18 CST
Grading Update 3: Midterm Exam grades ready. The grade average is 44.1 the median grade is 43. This is not too different than past grade distributions. Just saying. To see your grade, the grade distribution, or just to look at the aliases, click here. Remember that if the final exam grade is higher than the midterm grade the midterm grade will be replaced by the final exam grade.

1 November 2025, 18:00:03 CDT
Grading Update 2: Problem 1 graded, Problem 2 mostly graded. The exam grades should be available some time tomorrow. The next grading update will be posted by 18:00 standard time (yay!), probably earlier.

31 October 2025, 11:01:50 CDT
Linked recent material and upcomming sequential material to the lectures page.

What Was New
19 more items starting 31 October 2025, 10:52:37 CDT.

David M. Koppelman - koppel@ece.lsu.edu	Modified 2 Nov 2025 13:10 (1910 UTC)
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