EE 4755, Digital Design Using HDLs
When / Where / Details
Lecture slides and examples used in class.
The current status of the computers in
Room 2241 P.F. Taylor Hall. Updated every 10 minutes.
Instructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
Software manuals and information on Verilog.
Additional material on Verilog inference and synthesis.
The most accessed Web pages for this course over the
past three days.
Includes solutions. |
What's New
15 December 2025, 18:47:09 CST
Grading Update 6: Course grades posted to Workday
Student. Spoiler alert: no one failed. Thank you for
your effort in EE 4755, and have a good winter break!!
15 December 2025, 18:19:40 CST
Grading Update 5: Haven't chosen course grades yet.
When they are ready they will be posted to Workday Student.
They won't be posted on the Web (to save time). I'll post
an entry here when they are done. The next grading update
will be posted, I hope, in a half-hour or less.
15 December 2025, 15:01:02 CST
Grading Update 4: Final Exam grades
ready. The average is 49.9, the median a bit lower at 42.5.
The average is about the same as the midterm exam. Many did
well, but not enough. To see the distribution, your grade, or just
to peruse the aliases, click here. Grades for the last
homework will be sent, and then course grades.
The next grading update should be posted by 18:00 tonight.
What Was New
34 more items starting 14 December 2025, 17:47:58 CST.
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