EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2024: MWF 11:30-12:20 CT 1212 Taylor Hall
Fall 2024 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

What's Popular

The most accessed Web pages for this course over the past three days.

12 December 2024, 17:38:36 CST
Grading Update 0: Linked the Final Exam to the assignments and exams page. Grading will start late Friday or Saturday and Final Exam grades may be available by Sunday. The next grading update should be posted by Saturday about 18:00.

11 December 2024, 9:31:10 CST
Linked the Final Exam reveiw slides to the lectures page.

10 December 2024, 12:04:29 CST
In the solution shown to the 2021 Midterm Exam Problem 1 on the whiteboard for the optimized case, the select signal for the i[0],i[1] multiplexor should have been fmt[0]. That way if both fmt[0] and fmt[1] were 1, there would be no problem. Since there was no logic at the select signal of the first two multiplexors, the critical path would be 4 (two per mux).

What Was New
39 more items starting 8 December 2024, 17:58:30 CST.

David M. Koppelman - koppel@ece.lsu.edu	Modified 12 Dec 2024 17:40 (2340 UTC)
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