EE 4755, Digital Design Using HDLs
When / Where / Details
Lecture slides and examples used in class.
The current status of the computers in the back of Room 2241 P.F. Taylor Hall. Updated every 10 minutes.
Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).
Software manuals and information on Verilog.
Additional material on Verilog inference and synthesis.
The most accessed Web pages for this course over the past three days.
|David M. Koppelman - firstname.lastname@example.org||Modified 14 Dec 2021 12:03 (1803 UTC)|
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