EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2025: MWF 11:30-12:20 CT 1206 Taylor Hall
Fall 2025 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

What's Popular

The most accessed Web pages for this course over the past three days.

9 December 2025, 18:28:33 CST
The 2024 Final Exam solution now has a solution to all problems, except for the arrival time and critical path illustrations on Problem 2. Those probably won't be done until after the exam.

9 December 2025, 17:23:46 CST
Linked a 2024 Final Exam partial solution to the assignments and exams page. There is no solution to Problem 4 and the Problem 2 solution is incomplete. They will be added later.

7 December 2025, 16:30:34 CST
Linked the Homework 5 solution to the assignments and exams page. To help prepare for the exam look at the solution, including the "good" and fast versions.

What Was New
28 more items starting 5 December 2025, 14:48:25 CST.

David M. Koppelman - koppel@ece.lsu.edu	Modified 9 Dec 2025 18:29 (029 UTC)
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