EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2024: MWF 11:30-12:20 CT 1212 Taylor Hall
Fall 2024 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

What's Popular

The most accessed Web pages for this course over the past three days.

17 December 2024, 11:47:36 CST
Grading Update 4: Course Grades Available. The course letter grades have been posted, to see your click here and maybe refresh the page.

The winner of the best alias contest is Synthesizzle. It is relevant, playful, and best of all hard to pronounce.

Good luck and thank you for your effort in EE 4755!

16 December 2024, 18:01:11 CST
Grading Update 3: Everything graded. Course grades should be available tomorrow about noon, except those who are graduating who will find out in the usual way. Course work grades may be posted later tonight. The next grading update should be posted tomorrow by noon.

16 December 2024, 14:55:41 CST
Grading Update 2: Final Exam Grades Ready. The range was [77,6] with a median of 41 and a close by mean of 40.9. To find out your grade or at least try to guess the winner of the best alias contest click here. Grading of the last homework will start now. The next grading update may be posted roughly 18:00.

What Was New
43 more items starting 15 December 2024, 17:54:07 CST.

David M. Koppelman - koppel@ece.lsu.edu	Modified 17 Dec 2024 11:52 (1752 UTC)
Provide Website Feedback • Accessibility Statement • Privacy Statement