EE 4755, Digital Design Using HDLs

When / Where / Details

Fall 2025: MWF 11:30-12:20 CT 1206 Taylor Hall
Fall 2025 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

What's Popular

The most accessed Web pages for this course over the past three days.

Assignments and Exams

Includes solutions.
 Screenshot of design.
RSS Feed What's New
13 December 2025, 18:01:49 CST
Grading Update 2: Nothing graded yet. Grading may start tonight. The next grading update should be posted by about 18:00 tomorrow night.

12 December 2025, 15:46:37 CST
Grading Update 1: Linked the Final Exam to the assignments and exams page. Grading should start some time tomorrow, after the GPU final exam is graded. The next grading update (for this class) should be posted by about 18:00 tomorrow. Good luck on your other classes!

9 December 2025, 18:28:33 CST
The 2024 Final Exam solution now has a solution to all problems, except for the arrival time and critical path illustrations on Problem 2. Those probably won't be done until after the exam.

What Was New
30 more items starting 9 December 2025, 17:23:46 CST.

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David M. Koppelman - koppel@ece.lsu.edu
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