Selected Publications
Book and Book Chapters
Patents
Conference Papers
Journal Articles

R. Vaidyanathan and J. L. Trahan,
"Dynamic Reconfiguration: Architectures and Algorithms,"
Kluwer Academic/Plenum Publishers,
January 2004.

R. Vaidyanathan and J. L. Trahan,
"Dynamic Reconfiguration on the RMesh,"
Handbook
of Parallel Computing: Models, Algorithms and Applications,
S. Rajasekaran and J. Reif, eds., CRC Press, 2007.

R. Vaidyanathan, J. L. Trahan, and S. Rai,
"Introducing Parallel and Distributed Computing Concepts in Digital Logic,"
in
Topics in Parallel and Distributed Computing: Introducing Concurrency
in Undergraduate Courses, 1st edition, eds. S. K. Prasad et al.,
ElsevierMorgan Kaufman, 2015.

M. Feldman, A. ElAmawy and R. Vaidyanathan,
"Optical Slab Waveguide for Massive, HighSpeed Interconnects,"
US Patent 6,332,050, Dec. 2001.

M. Feldman, A. ElAmawy and R. Vaidyanathan,
"Optical Crossbar Switch,"
US Patent 6,792,175, Sept. 2004.

R. Vaidyanathan and M. C. Jordan,
"Configurable Decoder with Applications in FPGAs,"
US Patent 8,862,854, Oct. 2014.
US Patent 9,257,988, Feb. 2016.

R. Vaidyanathan and A. Ashrafi
"Architecture for Configuration of a Reconfigurable Integrated Circuit,"
Patent Application 20,160,299,872, Oct. 2016.

R. Vaidyanathan and A. B. Mansour
"Asynchronous Distributed Optical Mutual Exclusion Interconnect and Method,"
Patent Application 20,170,336,586, Nov. 2017.

U. Agrawal and R. Vaidyanathan,
"Efficient TotallyOrdered Subset Generation, with Application in Partial
Reconfiguration,"
Proc. The Reconfigurable Architectures Workshop (RAW),
International Parallel and Distributed Processing Symposium, 2017,
pp. 192201.

Y. BenAsher, E. Stien and R. Vaidyanathan,
"Combining Boolean Gates and Branching Programs in One Model can Lead to
Faster Circuits,"
Proc. The Reconfigurable Architectures Workshop (RAW),
International Parallel and Distributed Processing Symposium, 2017,
pp. 184191.

G. Sharma, R. Vaidyanathan, J. L. Trahan, C. Busch and S. Rai,
"O(log N)Time Complete Visibility for Asynchronous Robots with Lights,"
Proc. The International Parallel and Distributed Processing Symposium
(IPDPS), Orlando, 2017, pp. 513522.

G. Sharma, R. Vaidyanathan, J. L. Trahan, C. Busch and S. Rai,
"Complete Visibility for Robots with Lights in O(1) Time,"
Proc. 18th International Symposium Stabilization, Safety, and
Security of Distributed Systems (SSS), Springer LNCS 10083,
pp. 327345, 2016.

S. Wu, S. Wei, Y. Wang, R. Vaidyanathan and J. Yuan,
"Detection of Graph Structures via Communications over a Multiaccess Boolean
Channel,"
in Proc. IEEE International Symposium on Information Theory
(ISIT)
, 2015.

A. Ashrafi and R. Vaidyanathan,
"An Architecture for Configuring an EffBcient Scan Path for a Subset of
Elements,"
Proc. Reconfigurable Architectures Workshop (RAW),
International Parallel and Distributed Procesing Symposium Workshops (IPDPSW),
2015, pp. 144153.

R. Vaidyanathan, C. Busch, J. L. Trahan, G. Sharma and S. Rai,
"LogarithmicTime Complete Visibility for Robots with Lights,"
Proc. International Parallel and Distributed Processing Symposium
(IPDPS),
2015, pp. 375384.

G. Sharma, S. Rai, C. Busch, J. L. Trahan and R. Vaidyanathan,
"WorkEfficient Load balancing,"
Proc. 10th International Workshop on Scheduling and
Resource Management for Parallel and Distributed Systems, International
Conference on Parallel Processing, Minneapolis, pp. 2736, 2014.

S. Wu, S. Wei, R. Vaidyanathan and J. Yuan,
"Achievable Partition Information Rate over Noisy MultiAccess Boolean
Channel,"
Proc. IEEE International Symposium on Information Theory,
pp. 12061210, 2014, Hawaii.

S. Wu, S. Wei, R. Vaidyanathan and J. Yuan,
"Transmission of Partitioning Information over
NonAdaptive MultiAccess Boolean Channel,"
Proc. 48th Annual Conference on Information
Sciences and Systems (CISS), March 2014, Princeton, NJ.

R. Vaidyanathan and P. Vinukonda,
"On Running Windowed Image Computations on a Pipeline,"
Proc. Workshop on Advances in Parallel and Distributed Computation
Models, IPDPS, 2012

G. Sharma, C. Busch, R. Vaidyanathan, S. Rai, and J. Trahan,
"An Efficient Transformation for Klee's Measure Problem in the
Streaming Model,"
Proc. 24th Canadian Conference on Computational Geometry,
2012, pp. 9196.

M. C. Jordan and R. Vaidyanathan,
"MU Decoders: A Class of Fast and Efficient Configurable Decoders,"
Proc. Reconfigurable Architectures Workshop,
IPDPS, 2010.

K. Roy, R. Vaidyanathan, J. L. Trahan,
"InputQueued Switches with Logarithmic Delay: Necessary Conditions and
a Reconfigurable Scheduling Algorithm,"
Proc. Symp. on Architectures for Networking and Communications
Systems, 2008, pp. 121122.

S. L. Bishop, S. Rai, B. Gunturk, J. L. Trahan, R. Vaidyanathan,
"Reconfigurable Implementation of Wavelet Integer Lifting Transforms for
Image Compression,"
Proc. ReConFig 06,
Sept. 2006, pp. 2022.

R. Vaidyanathan and K. Sethuraman
"On Mapping Multidimensional Weak Tori on Optical Slab Waveguides,"
Proc. International Conference on Parallel Processing
, 2005, pp. 219226.

K. Roy, R. Vaidyanathan and J. L. Trahan,
"Configuring the Circuit Switched Tree for Multiple Width Communications,"
Proc., Workshop on Advances in Parallel & Distributed Computational Models
, 2005.

K. Roy, J. L. Trahan and R. Vaidyanathan,
"Configuring the Circuit Switched Tree for WellNested and Multicast
Communication,"
Proc. 16th IASTED International Conference on Parallel and Distributed Computing
and Systems,
pp. 392397, 2004.

H. M. ElBoghdadi, R. Vaidyanathan, J. L. Trahan and S. Rai,
"On Designing Implementable Algorithms for the Linear Reconfigurable
Mesh,"
Proc. Int. Conf. on Parallel and Distributed Processing
Techniques and Applications,
pp. 241246, 2003.

H. P. Dharmasena and R. Vaidyanathan,
"Fault Tolerance in Multiple Bus Networks with Unbalanced Resource
Utilization,"
Proc
Int. Conf. on Parallel and Distributed Processing
Techniques and Applications,
pp. 246252, 2003.

N. Srivastava, J. L. Trahan, R. Vaidyanathan, and S. Rai
"Adaptive Image Filtering using RunTime Reconfiguration,"
in
Proc. 10th Reconfigurable Architectures Workshop, 2003,
included in Procs. 17th
International Parallel and Distributed Processing Symposium,
2003, p. 180.

S. Wu, S. Wei, Y. Wang, R. Vaidyanathan and J. Yuan,
"Asymptotic ErrorFree Partitioning over Noisy Boolean Multiaccess Channels,"
IEEE Transactions on Information Theory,
vol. 61, no. 11, November 2015, pp. 61686181.

G. Sharma, C. Busch, R. Vaidyanathan, S. Rai, and J. Trahan,
"Efficient Transformations for Klee's Measure Problem in the
Streaming Model,"
Computational Geometry: Theory and Applications,vol. 48, issue 9, 2015,
pp. 688702.

S. Wu, S. Wei, Y. Wang, R. Vaidyanathan and J. Yuan,
"Partition Information and its Transmission over
Boolean MultiAccess Channels,"
IEEE Transactions on Information Theory,
vol. 61, no. 2, Feb. 2015, pp. 10101027.

R. Vaidyanathan, P. Vinukonda and A. Lessing,
"Pipelined Execution of Windowed Image Computations,"
International Journal of Netwoking and Computing
vol. 3, no. 1, pp. 7597, Jan. 2013.

M. Feldman, A. ElAmawy, A. Srivastava and R. Vaidyanathan,
"Adjustable WollastonLike Prisms,"
Review of Scientific Instruments, vol. 77, 2006.

K. Roy, R. Vaidyanathan and J. L. Trahan
"Routing Multiple Width Communications on the Circuit Switched Tree,"
International Journal of Foundations of Computer Science, vol. 17,
No. 2, April 2006, pp. 271285.

H. P. Dharmasena and R. Vaidyanathan,
"The Mesh with Binary Tree Networks: An Enhanced Mesh with Low BusLoading,"
The Journal of Interconnection Networks,
vol.5, no.2, June 2004, pp.131150.

H. P. Dharmasena and R. Vaidyanathan,
"Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree
Algorithms,"
IEEE Transactions on Computers, vol. 53, no. 12, December 2004, 00. 15351546.

R. Vaidyanathan, J. L. Trahan and Cm. Lu,
"Degree of Scalability:
Scalable Reconfigurable Mesh Algorithms for Multiple Addition
and MatrixVector Multiplication,"
Parallel Computing,
2003, vol. 29, no. 1, pp. 95109.

J. A. FernandezZepeda, R. Vaidyanathan, and J. L. Trahan,
"Using Bus Linearization to Scale the Reconfigurable Mesh,"
Journal of Parallel & Distributed Computing,
2002, vol. 62, no. 4, pp. 495516.

J. L. Trahan and R. Vaidyanathan,
"Scaling Multiple Addition
and Prefix Sums on the Reconfigurable Mesh,"
Information Processing Letters
2002, vol. 82, no. 6, pp. 277282.
R. Vaidyanathan
Elaine T. and Donald C. Delaune Distinguished Associate Professor
School of Electrical Engineering and Computer Science
Louisiana State University
Baton Rouge, LA 708035901
Phone: (225) 5785238
Fax: (225) 5785200
Email: