EE 4755, Digital Design Using HDLs
When / Where / Details
Lecture slides and examples used in class.
Instructions on how to use the software, including the Verilog
simulation, Verilog synthesis, and Emacs (text editor).
Software manuals and information on Verilog.
Additional material on Verilog inference and synthesis.
20 September 2017, 16:06:38 CDT
The homework assignment available before 16:06 today
had a small error in the description of functions a(x) and
ai(j). In both cases an a1 term
was missing. The assignment has been corrected. The module
which implements ai(j), was always correct.
19 September 2017, 14:26:27 CDT
Linked the Homework 1 solution
to the assignments and exams page.
18 September 2017, 18:51:44 CDT
Homework 2 assigned, due 25 September 2017
What Was New
9 more items starting 11 September 2017, 14:25:11 CDT.