EE 4755, Digital Design Using HDLs


When / Where / Details

Fall 2023: MWF 11:30-12:20 CT 1240 Taylor Hall
Fall 2023 Syllabus

Current Lectures

Lecture slides and examples used in class.

Computer Status

The current status of the computers in Room 2241 P.F. Taylor Hall. Updated every 10 minutes.

Procedures

Instructions on how to use the software, including the Verilog simulation, Verilog synthesis, and Emacs (text editor).

References

Software manuals and information on Verilog.

Study Guide

Additional material on Verilog inference and synthesis.

Grades

What's Popular

The most accessed Web pages for this course over the past three days.

Assignments and Exams

Includes solutions.
Screenshot of design.
RSS Feed What's New
11 December 2023, 14:59:18 CST
Grading Update 4: Course Grades ready. To view homework grades, the coursework average, and letter grades, click here. Thank you for your effort in this course and have a good winter break!

11 December 2023, 13:19:33 CST
Grading Update 3: Final Exam Grades Ready. The median is 42, which is much better than the midterm exam where the median was 22.5. The average is also much better. To find the most important grade click here. Course grades should be available later today.

10 December 2023, 18:46:01 CST
Grading Update 2: Problems 1-3 graded. The final exam grades will be available some time tomorrow. Course grades will probably be available tomorrow too.

What Was New
34 more items starting 9 December 2023, 18:28:50 CST.


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