EE 7700-3: Architectures and Algorithms for DSP

Call No: 8499                              Fall 2004

Course material (handouts, ...)

Title: EE 7700-3: Architectures and Algorithms for DSP
Call No.: 8499
Professor:    J. (Ram) Ramanujam, 345 EE Bldg., 578-5628 (Email: jxr AT ece DOT lsu DOT edu)
Time, Place: 10:40 - 11:30 MWF in Room 145 EE Building
  • Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, 1999.
  • Recent papers from the literature
Prerequisites:    Graduate standing.
Digital signal processing is an area which is highly expansive and it is a part of many modern systems. Examples of systems having a lot of signal processing are mobile communication systems and CD-players while examples of algorithms ar different types of coding, filtering, image processing, etc. There is often an requirement that the signal processing has to be performed in real time, limiting the possibility of using a computer (or with general-purpose processors); additional requirements on throughput and/or power dissipation will demand application specific processors with higher performance measures.

This course will give insight in how to get from an algorithm to an application specific solution fulfilling the requirements. The main part will cover the area of application specific solutions, ASICs, but general purpose processors will also be covered. The goal of the course is to teach systematic design of digital signal processors.

Description and Topics:
1. High-Level Architecture Transformations: Characteristics and representations of signal processing programs: signal flow graphs, data-flow graphs and dependence graphs, iteration bound, pipelining and parallel processing for high-speed and low-power, high-level transformations such as retiming, unfolding, folding, systolic array design.

2. High-Level Algorithm Transformations: Strength reduction in parallel filters, pipelined and parallel IIR digital filters.

3. Implementation Styles: Arithmetic processors for signal processing using bit-level and multi-bit level pipelining, Bit-parallel, bit-serial, and digit-serial structures for addition and multiplication. Use of canonic signed digit, carry-save, distributed arithmetic, redundant number based arithmetic architectures. Numerical strength reduction.


  • Termpaper and Presentation 30%
  • Test 30%
  • Final 40%