Ashok Srivastava

Wilbur D. and Camille V. Fugler, Jr. Professor 

Address:

      Louisiana State University
      Division of Electrical & Computer Engineering
      Baton Rouge, LA 70803-5901

Tel:      225-578-5622
Fax:     225-578-5200
E-mail:  ashok@ece.lsu.edu; eesriv@lsu.edu

Research Interests:

 

Low Power VLSI Circuit Design and Testability (Digital, Analog and Mixed-Signal); Noise in Devices and VLSI Circuits; Nanoelectronics (Non-classical Device Electronics with focus on Carbon Nanotube, Graphene and other 2D materials for Integration with Sub-nanometer CMOS Technology Nodes and Emerging Integrated Electronics; RF Integrated Circuits; Semiconductor Devices Modeling; Radiation-hard Integrated Circuits; and Low-Temperature Electronics

 

Biographical Sketch:

 

Dr. Ashok Srivastava received his M.Sc. (Physics) degree with specialization in Advanced Electronics from University of Lucknow, India, in 1968. He obtained M.Tech. and Ph.D. degrees in Solid State Physics and Semiconductor Electronics area from Indian Institute of Technology, Delhi in 1970 and 1975, respectively. He joined the Department of Electrical & Computer Engineering of Louisiana State University, Baton Rouge in 1990 as an Associate Professor and currently is Wilbur D. and Camille V. Fugler, Jr., Professor of Engineering. In year 2011, he held visiting appointments at the Institute of Electrical Engineering NanoLab, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland; Katholiek Universiteit/Inter-university Microelectronics Center (IMEC), Leuven, Belgium; Indian Institute of Information Technology (IIIT), Allahabad; and in year 2001 at the Philips Research Laboratory, Eindhoven, The Netherlands. His other past appointments include Central Electronics Engineering Research Institute, Pilani, India (1975-84), Birla Institute of Technology and Science, Pilani, India (1975); North Carolina State University, Raleigh (1985-86); State University of New York, New Paltz (1986-90); University of Cincinnati, Cincinnati (1979); University of Arizona, Tucson (1979-80), Kirtland Air Force Base, New Mexico (Summer 1996); and Jet Propulsion Laboratory/California Institute of Technology, Pasadena (Summer 2004).

 

He is the recipient of the prestigious 1979-1980 UNESCO Fellowship Award and Dean College of Engineering 1994 Teaching Award, Louisiana State University. He has 1 US patent and several technology disclosures. He is the author of more than 150 technical papers, including conference proceedings book chapters and a book on Nanoelectronics. He has graduated 40 students in Electrical Engineering including 7 PhDs who are employed by academic institutions, VLSI chip design and semiconductor companies across the globe. He has also supervised many MS (EE) students with non-thesis and project options. He has many professional presentations including invited talks. He is reviewer of numerous international journal papers and books, examiner of overseas PhD dissertations and has served on NSF review panels and advisory board of NSF CREST and RISE of one of the US universities and program committees of international conferences. He serves on the Editorial Review Board of the International Journal of Nanotechnology and Molecular Computation (IJNMC), Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology published by the Scientific Research, USA. He has been awarded grants and contracts from federal, state, industry and foundations. He is a Senior Member of IEEE, Electron Devices, Circuits and Systems, and Solid-State Circuits Societies, and Member of SPIE and ASEE.

 

Current PhD Students:

 

Md. Shamiul Fahad (BS 2009, Islamic University of Technology (IUT), Bangladesh), “Carbon Electronics and CMOS VLSI (GNR Tunnel FETs),” joined in spring 2012, passed PhD qualifying (spring 13).

K. M. Mohsin (BS 2011, Bangladesh University of Engineering and Technology), “Carbon Electronics and CMOS VLSI (Thermal Modeling of CNT and GNR Interconnects),” joined in spring 2012, passed PhD qualifying (spring 13).

Yasser Mohammadi Banadaki (MS 2007, Shahid Beheshti University, Iran), “Graphene Transistors and CMOS VLSI,” joined in fall 2012, passed PhD qualifying (spring 13).

XinLu Chen, (BS 2012, Shadong University, China), “2D Materials-based Electronics and CMOS VLSI,” joined in fall 2014.


Zhou Zhao (MS 2014, University of Electronic Science & Technology, China), “Signal Transmission and Power Integrity in VLSI Circuits,” joined in fall 2014.

 

Undergraduate Courses: EE3001: Electronics II; EE 4242: VLSI Design; EE 4240: Linear Circuit Design; EE 4250: Digital Integrated Circuit

 

Graduate Courses: EE 7242: VLSI Systems; EE 7248: Mixed-Signal Integrated Circuit Design; EE7000: Nanoelectronics; EE7230: Physics of Device Electronics; EE 7246: Integrated Sensors and Actuators; and EE 7000: Wireless Communications: System Design and (VLSI) Circuit Implementation

 

Book: Ashok Srivastava, Jose M. Marulanda, Yao Xu and Ashwani K. Sharma, “Carbon-based Electronics: Transistors and Interconnects at the Nanoscale”, Pan Stanford Publishing, Singapore, (in press 2014, available 2015 in print).


Journal Publications (Recent):


1. S. Varshney, M. Goswami, B.R. Singh, and A. Srivastava, “Low power-variable resolution analog-to-digital converter,” J. Low Power Electronics, vol. 10, no. 2, pp. 236-246, June 2014.


2. K. M. Mohsin, A. Srivastava, A. K. Sharma and C. Mayberry, “A thermal model for carbon nanotube interconnects,” nanomaterials (Special Issue: CNT based Nanomaterials), Vol. 3(2), pp. 229-241, 2013.


3. A. Srivastava, Y. Xu, Y. Liu, A.K. Sharma and C. Mayberry, “CMOS LC voltage controlled oscillator design using carbon nanotube wire inductors,” ACM J. Emerging Technologies in Computing Systems (Special Issue), vol. 8, no. 3, Article 15, pp. 15.1-15.9, August 2012.


4. R. Soundararajan and A. Srivastava, “A programmable oversampling CMOS delta-sigma analog-to-digital converter for low-power interface electronics,” J. Low Power Electronics, vol. 8, no. 3, pp. 336-346, June 2012.


5. Y. Liu and A. Srivastava, “CMOS phase-locked loop circuits and hot carrier effects,” J. Low Power Electronics, vol. 8, no. 3, pp. 304-316, June 2012.


6. R. Soundararajan, A. Srivastava and S. Yellampalli, “Delta-IDDQ testing of a digital-to-analog converter considering process variation effects,” Circuits and Systems, vol. 2, pp. 133-138, 2011,

DOI: 10.4236/cs.2011.23020 Published online July 2011, Scientific Research, U.S.A.


7. Y. Liu, A. Srivastava and Y. Xu, “Switchable PLL frequency synthesizer and hot carrier effects,” Circuits and Systems, vol. 2011, no. 2, pp. 45-52, January 2011, DOI: 10.4236/cs.2011.21008, Published online January 2011, Scientific Research, U.S.A.


8. A. Srivastava, Y. Xu and A. K. Sharma, “Carbon nanotubes for next generation very large scale integration interconnects,” J. Nanophotonics, (invited paper - online), special section on carbon nanotubes, vol. 4, 041690 (17 May 2010), pp. 1-26, 2010. DOI: 10.1117/1.3446896.


9. Y. Xu and A. Srivastava, “A model for carbon nanotube interconnects,” Int. J. of Circuit Theory and Applications, vol. 38, Issue 6, pp. 559-575, 2010. Published online: 2 March 2009 by Wiley InterScience, DOI: 10.1002/cta.587, pp. 1-17, 2009.

10.Y. Xu, A. Srivastava and A.K. Sharma, "Emerging carbon nanotube electronic circuits, modeling and performance," VLSI Design (invited paper - online), vol. 2010, Article ID 864165, pp. 1-8, 2010. DOI: 10.1155/2010/864165.

Conference Publications (Recent):

1. K.M. Mohsin, A. Srivastava, A.K. Sharma and C. Mayberry, “Characterization of MWCNT VLSI interconnects with self-heating induced scatterings,” Proc. of 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 368-373, (9-11 July, 2014 Tampa, FL).


2. S. Chen, Y. Zhang, L. Peng, J. Ardonne, S. Irving and A. Srivastava, “Increasing of-chip bandwidth in multi-core processors with switchable pins,” in Proc. of The 41st International Symposium on Computer Architecture (ISCA 2014), pp. 1-12, (Minneapolis, MN, June 14-18, 2014).


3. A. Srivastava, Y.M. Banadaki and Md. S. Fahad, “Dielectrics for graphene transistors for emerging integrated circuits,” IEEE EDS/ECS International Symposium on Dielectrics for Nanosystems, 225th ECS Meeting (May 11-16, 2014, Orlando, FL), ECS Transactions, Chapter 9, vol. 61, pp. 351-361, invited paper.


4. Y. M. Banadaki, K. M. Mohsin and A. Srivastava, “A graphene field-effect transistor for high-temperature sensing applications,” SPIE Smart Structures/NDE: Nano-, Bio-, and Info-Tech Sensors and Systems: SSNO6, pp. 1-7, (March 9-13, 2014, San Diego, CA), invited paper.

5. K.M. Moshin, Y.M. Banadaki and A. Srivastava, “Metallic Single-walled carbon nanotube based temperature sensor,” SPIE Smart Structures/NDE: Nano-, Bio-, and Info-Tech Sensors and Systems: SSNO6, pp. 1-7, (March 9-13, 2014, San Diego, CA), invited paper.

6. Md. Fahad, A. Srivastava, A.K. Sharma and C. Mayberry, “Current transport in grapheme tunnel field effect transistor under constant electric field,” SPIE 2013 Nanoscience+Engineering: Carbon Nanotubes, Graphene, and Associated Devices VI (OP109), Proc. of SPIE, vol. 8814, 8 pages (25-29 August 2013, San Diego, CA).

7. Y. M. Banadaki and A. Srivastava, “A novel graphene nanoribbon field effect transistor for integrated circuit design,” Proc. of The 56th IEEE Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2013), 4 pages (August 4-7, 2013, Columbus, OH).


8. M. S. Fahad, A. Srivastava and A.K. Sharma, C. Mayberry, “Current transport in graphene tunnel field effect transistor for RF integrated circuits,” Proc. IEEE MTT-S International Wireless Symposium, 4 pages (13-18 April 2013, pp. 1-4, Beijing, China).


9. A. Srivastava and R. Soundararajan, “Testing of Trusted CMOS data converters,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2012), pp. 350-355 (August 19-21, 2012, University of Massachusetts, Amherst, MA).

10. A. Srivastava, Y. Xu, A.K. Sharma and C. Mayberry, “Electronic current transport in CNT-FETs for operation in ballistic region,” Proc. SPIE Conference 8344: Nano-, Bio-, and Info-Tech Sensors and Systems, vol. 8344, pp. 83440O-1 to 83440O-10 (San Diego, March 12-15, 2012).


11. A. Srivastava, “Transistor and Interconnect Modeling for Design of Carbon Nanotube Integrated Circuits,” in Proc. 19th International Conference on Mixed Design of Integrated Circuits and Systems, (May 24-26, 2012, Warsaw, Poland), invited paper (Plenary Session).


12. A. Srivastava, Y. Xu, Y. Liu, A.K. Sharma and C. Mayberry, “CMOS LC voltage-controlled oscillator design using multiwall carbon nanotube wire conductor,” in Proc. IEEE International Symposium on Electronic System Design, (Bhubaneswar, India, December 20-22, 2010). The paper received the Best Paper Award.


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