The 18th Reconfigurable Architectures
Workshop (RAW 2011) will be held in Anchorage, Alaska, USA in May 2011. RAW
2011 is associated with the 25th Annual International Parallel &
Distributed Processing Symposium (IPDPS 2011) and is sponsored by the IEEE
Computer Society's Technical Committee on Parallel Processing. The workshop is
one of the major meetings for researchers to present ideas, results, and
on-going research on both theoretical and practical advances in Reconfigurable
Computing.
Run-Time Reconfiguration & Adaptive
Computing:
Architectures, Algorithms, Technologies
Run-Time and Dynamic Reconfiguration are characterized by the ability of
underlying hardware architectures or devices to rapidly alter (on the fly) the
functionalities of its components and the interconnection between them to suit
the problem. Key to this ability is reconfiguration handling and speed. Though
theoretical models and algorithms for them have established reconfiguration as
a very powerful computing paradigm, practical considerations make these models
difficult to realize. On the other hand, commercially available devices (such
as FPGAs and new coarse-/multi-grain devices) appear to have more room for
exploiting run-time reconfiguration (RTR). An appropriate mix of the
theoretical foundations of dynamic reconfiguration, and practical
considerations, including architectures, technologies and tools supporting RTR
is essential to fully reveal and exploit the possibilities created by this
powerful computing paradigm. RAW 2011 aims to provide a forum for creative and
productive interaction between all these disciplines.
Topics of Interest
Authors are invited to submit manuscripts of original
unpublished research in all areas of dynamic and run-time reconfiguration
(foundations, algorithms, hardware architectures, devices, systems-on-chip
(SoC), technologies, software tools, and applications). The topics of interest
include, but are not limited to:
Models & Architectures ·
Theoretical Interconnect
·
RTR Models and
Systems ·
RTR Hardware Architectures ·
Optical
Interconnect Models ·
Simulation and Prototyping · Bounds and Complexity Issues |
Algorithms & Applications · Algorithmic Techniques · Mapping Parallel Algorithms · Distributed Systems & Networks · Fault Tolerance Issues · Wireless and Mobile Systems ·
Automotive
Applications ·
Infotainment &
Multimedia ·
Biology Inspired Applications |
Design, Technologies & Tools ·
Configurable
Systems-on-Chip ·
Energy Efficiency
Issues ·
Devices and
Circuits ·
Reconfiguration
Techniques ·
High Level Design
Methods · System Support · Adaptive Runtime Systems · Organic Computing |
Important Dates:
Submission deadline: December
24, 2010
Notification of acceptance: February 7, 2011
Camera-ready papers due: February 21, 2011
Submission (Closed):
Authors should submit their
paper through the
EDAS Conference Management System. You can
register for
an EDAS Account here.
All
manuscripts will be reviewed by at least three members of the program
committee. Submissions should be a complete manuscript (not to exceed 8 pages
of single spaced text, including figures and tables) or, in special cases, may
be a summary of relevant work. Submissions should be in pdf-format (preferred),
or alternatively in Postscript (level 2) format. Templates for paper
preparation can be found at: http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceTemplates.html
IEEE CS Press
will publish the IPDPS symposium and workshop abstracts as a printed volume.
The complete symposium and workshop proceedings will also be published by IEEE
CS Press as a CD-ROM disk.
Organization:
Workshop Chair: Jürgen Becker, Karlsruhe Institute of
Technology - KIT, Germany
becker@kit.edu
Program Co Chairs: Pascal Benoit, LIRMM, Montpellier, France
pascal.benoit@lirmm.fr
René
Cumplido, INAOE, Puebla, México
rcumplido@inaoep.mx
Steering Chair: Viktor K. Prasanna,
University of Southern California, USA
Publicity Chair (
vaidy@ece.lsu.edu
Publicity Chair (Europe, Asia): Reiner Hartenstein,
Program Committee: