8.00
- 8.15: Welcome & Opening
Jürgen
Becker, Universität Karlsruhe (TH), Germany
Serge Vernalde, IMEC,
8.15
- 9.00: Opening Keynote
Xilinx, Inc.;
Title: “Of Wires and Gates”
9.00
- 10.00: Session 1 Hardware Architectures I
Chair: J. Becker - Universität Karlsruhe (TH),
Eric Swankoski,
Richard Brooks
Applied Research Laboratory,
Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin
Department of Computer Science &
Engineering,
Title: “A
Parallel Architecture for Secure FPGA Symmetric Encryption”
Ashutosh S. Dhodapkar, James E. Smith
Title: “Tuning Reconfigurable Microarchitectures
for Power Efficiency”
Sakir Sezer, Ciaran Toal
Queen's University
Title: “A Reconfigurable Tag Computation Architecture
for Terabit Packet Scheduling”
10.00
- 10.30: Coffee
Break
10.30
- 12.10: Session 2 Run-time Reconfiguration
Chair: S. Vernalde - IMEC,
Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
Title: “A New Approach for On-line Placement on
Reconfigurable Devices”
Emanuele Lattanzi, Alessandro Bogliolo
STI - University of Urbino, Italy
Aman Gayasen, Mahmut Kandemir, Vijaykrishnan
Narayanan
Penn State University, USA
Luca Benini
DEIS -
Title: “Improving Java Performance by Dynamic Method
Migration on FPGAs”
Michael Ullmann, Bjoern Grimm, Michael Huebner, Juergen Becker
ITIV,
Title: “An FPGA Run-Time System for Dynamical On-Demand
Reconfiguration”
Sebastian Lange, Martin Middendorf
Department of Computer Science,
Title: “Models and Reconfiguration Problems for Multi
Task Hyperreconfigurable Architectures”
University
Wolfram Hardt
Title: “Runtime Reconfigurable Interfaces - The RTR-IFB
Approach”
12.10
- 13.40: Lunch Break
13.40
- 15.00: Session 3 System Design
Chair: P. Diniz,
Esam ElDin Mohamed Aly El-Araby, Mohamed Taher, Tarek El-Ghazawi, Nikitas Alexandridis
The
Kris Gaj
David Caliga
SRC Computers
Title: “System-Level Parallelism and Throughput
Optimization in Designing Reconfigurable Computing Applications”
Patrick Schaumont, Kazuo Sakiyama,
Alireza Hodjat,
Electrical Engineering Department,
Title: “Embedded Software Integration of Coarse-grain
Reconfigurable Systems”
V. Kalenteridis, H. Pournara, I. Pappas, S.
Nikolaidis
Aristotle
K. Siozios, K. Tatas
Title: “An Integrated FPGA Design Framework: Custom
Designed FPGA Platform and Application Mapping Toolset Development”
15.00
- 15.30: Coffee Break
15.30
- 16.50: Session 4 Reconfiguration Technologies
Chair: A. Mukherjee –
Michael Huebner, Michael Ullmann, Florian Weissel, Juergen Becker
ITIV,
Title: “Real-time Configuration Code Decompression for
Dynamic FPGA Self-Reconfiguration”
Renqiu Huang, Ranga Vemuri
Title: “Forward-looking macro generation and relational
placement during high level synthesis to FPGAs”
Doris Ching, Patrick Schaumont,
Electrical Engineering Department,
Title: “Integrated Modelling and Generation of A Reconfigurable Network-On-Chip”
HNI,
Christophe Bobda
Title: “Dynamic Reconfiguration of Distributed Arithmetic
Controllers: Design Space Exploration and Trade-off Analysis”
16.50
- 17.05: Short Break
17.05
- 18.05: Session 5 Placement & Routing
Chair:
Manish Handa, Ranga Vemuri
Title: “Hardware Assisted Two Dimensional Ultra Fast
Placement”
Heiko Kalte, Mario Porrmann, Ulrich Rückert
Heinz Nixdorf Institute,
Title: “System-on-Programmable-Chip Approach Enabling
Online Fine-Grained 1D-Placement”
Cristinel Ababei, Kia Bazargan
Title: “Non-Contiguous Linear Placement for
Reconfigurable Fabrics”
18.05:
Dinner
TCPP reception in the evening, with a talk on the
Virginia Tech 10 TeraFlop X-Cluster machine
8.00
- 8.30: Keynote II
Title: “Impacting Education Using FPGAs”
8.30
- 10.10: Session 6 Hardware Architectures II
Chair: R. Hartenstein, Kaiserslautern University of Technology, Germany
Tyson S. Hall, Christopher M. Twigg, Paul Hasler, David V.
Georgia Institute of
Title: “Developing Large-Scale Field-Programmable
Analog Arrays”
Janusz A. Starzyk, Yongtao Guo
Title: “Dynamically Reconfigurable Neuron Architecture
for the Implementation of Self-Organizing Learning Array”
Adronis Niyonkuru, Hans
Christoph Zeidler
Universitaet der
Title: “Designing a Runtime Reconfigurable Processor
for General Purpose Applications”
Nazar A. Saqib, Francisco Rodríguez-Henríquez,
Arturo Díaz-Pérez
Computer Science
Section, Electrical Engineering, Instituto Politécnico Nacional No. 2508,
Title: “A Parallel Architecture for Fast Computation of
Elliptic Curve Scalar Multiplication over GF(2m)”
Shigeyuki Takano
Title: “Adaptive Processor: A Model of Stream
Processing”
10.10
- 10.40: Coffee Break
10.40
- 12.00: Session 7 Fault Tolerance
Chair: R. Vaidyanathan –
Huang, M. B. Tahoori,
F. Lombardi
Northeastern
Title: “Probabilistic Analysis of Fault Tolerance of
FPGA Switch Block Array”
Michael Caffrey,
Eric Johnson, Nathan Rollins, Michael Wirthlin
Title: “Dynamic Reconfiguration for Management of
Radiation-Induced Faults in FPGAs”
Lilian Bossuet, Guy Gogniat
Université de Bretagne Sud, France
Wayne Burleson
Title: “Dynamically Configurable Security for SRAM FPGA
Bitstreams”
Christian F. Silva, Alice M. Tokarnia
School of Electrical and Computing Engineering –
UNICAMP,
Title: “RECASTER: Synthesis of Fault-Tolerant Embedded System Based
on Dynamically Reconfigurable FPGAs”
12.00
- 13.30: Lunch Break
13.30
- 14.00: Invited Contribution
Klaus Waldschmidt
Title: ”Adaptive System Architectures”
14.00
- 15.00: Session 8 Coarse-Grain Models
Chair: S. Vernalde - IMEC,
Paul M. Heysters,
Gerard K. Rauwerda, Gerard J.M. Smit
Title: “Implementation of a HiperLAN/2 Receiver on the
Reconfigurable Montium Architecture”
Frank Hannig, Hritam Dutta, Juergen Teich
Title: “Mapping of Regular Nested
Yosi Ben-Asher
Gady Haber
IBM
Title: “Overlapping Memory Operations with Circuit
Evaluation in Reconfigurable Computing”
15.00
- 15.30: Coffee Break
15.30
- 16.50: Session 9 Arithmetic
Chair: D.
Bouldin,
Gokul Govindu, Seonil Choi, Viktor Prasanna
Vikash Daga, Sridhar Gangadharpalli,
Sridhar V.
Satyam Computer
Services Ltd.
Title: “A High-Performance and Energy-efficient
Architecture for Floating-point based LU Decomposition on FPGAs”
Gokul Govindu, Seonil Choi, Viktor Prasanna
Title: “Analysis of High-performance Floating-point
Arithmetic on FPGAs”
Sami Khawam, Tughrul Arslan
The University of
Fred Westall
EPSON
Title: “Synthesizable Reconfigurable Array Targeting
Distributed Arithmetic for System-on-Chip Applications”
Mitchell J. Myjak,
José G. Delgado-Frias
Title: “Pipelined Multipliers for Reconfigurable
Hardware”
16.50
- 17.05: Short Break
17.05
- 18.05: Session 10 Application & Mapping
Chair: Sakir Sezer, Queen´s University,
Al Strelzoff
Cadence Design Systems
Title: “Functional Programming for Reconfigurable
Arrays”
Kazuyuki Maruo,
Masayoshi Ichikawa
Advantest Laboratories Ltd.
Naoto Miyamoto, Leo Karnan,
Koji Kotani, Tadahiro Ohmi
Title: “A Dynamically-Reconfigurable Image Recognition
Processor”
Manoj Kumar A, Jayaram Bobba, Manimegalai, Kamakoti V
Indian
Title: “MemMap-pd: Performance
Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays”
18.05
- 18.15: Closing Remarks