`default_nettype none
module minmax2p1
#( int w = 4 )
( output uwire [w-1:0] min, max,
input uwire [w-1:0] a0, a1 );
uwire lt;
compare_lt #(w) clt(lt, a0, a1);
mux2 #(w) mn(max,lt,a0,a1);
mux2 #(w) mx(min,lt,a1,a0);
endmodule
module compare_lt
#( int w = 31 )
( output uwire lt,
input uwire [w-1:0] a0, a1 );
assign lt = a0 <= a1;
endmodule
module mux2
#( int w = 3 )
( output uwire [w-1:0] x,
input uwire s,
input uwire [w-1:0] a0, a1 );
assign x = s ? a1 : a0;
endmodule
module minmax2
#( int w = 10 )
( output uwire [w-1:0] min, max,
input uwire [w-1:0] a0, a1 );
assign { min, max } = a0 <= a1 ? { a0, a1 } : { a1, a0 };
endmodule
module minmax4
#( int w = 20 )
( output uwire [w-1:0] min, max,
input uwire [w-1:0] a[4] );
uwire [w-1:0] lomin, lomax, himin, himax;
minmax2 #(w) mlo( lomin, lomax, a[0], a[1] );
minmax2 #(w) mhi( himin, himax, a[2], a[3] );
min2 #(w) m1( min, lomin, himin );
max2 #(w) m2( max, lomax, himax );
endmodule
module minmax8
#( int w = 12 )
( output uwire [w-1:0] min, max,
input uwire [w-1:0] a[8] );
uwire [w-1:0] lomin, lomax, himin, himax;
minmax4 #(w) mlo( lomin, lomax, a[0:3] );
minmax4 #(w) mhi( himin, himax, a[4:7] );
min2 #(w) m1( min, lomin, himin );
max2 #(w) m2( max, lomax, himax );
endmodule
module min2
#( int w = 10 )
( output uwire [w-1:0] min,
input uwire [w-1:0] a0, a1 );
assign min = a0 < a1 ? a0 : a1;
endmodule
module max2
#( int w = 10 )
( output uwire [w-1:0] max,
input uwire [w-1:0] a0, a1 );
assign max = a0 < a1 ? a1 : a0;
endmodule
cadence
module testbench;
localparam int npsets = 3; localparam int pset[npsets] =
'{ 2, 4, 8 };
int t_errs; initial begin t_errs = 0; end
final $write("Total number of errors: %0d\n",t_errs);
uwire d[npsets:-1]; assign d[-1] = 1;
for ( genvar i=0; i<npsets; i++ )
testbench_n #(pset[i]) t2( .done(d[i]), .tstart(d[i-1]) );
endmodule
module testbench_n
#( int n = 5 )
( output logic done, input uwire tstart );
localparam int w = 13;
localparam int ntests = 100;
logic [w-1:0] a[n], sa[n];
uwire [w-1:0] min, max;
if ( n == 2 )
minmax2p1 #(w) mm( min, max, a[0], a[1] );
else if ( n == 4 )
minmax4 #(w) mm( min, max, a );
else if ( n == 8 )
minmax8 #(w) mm( min, max, a );
int n_err_min, n_err_max;
initial begin
done = 0;
wait( tstart );
n_err_min = 0;
n_err_max = 0;
for ( int i=0; i<ntests; i++ ) begin
logic [w-1:0] shadow_min, shadow_max;
for ( int i=0; i<n; i++ ) a[i] = {$random};
sa = a; sa.sort();
shadow_min = sa[0];
shadow_max = sa[n-1];
#1;
if ( min !== shadow_min ) begin
n_err_min++;
if ( n_err_min < 5 )
$write("Error n=%0d min %d != %d (correct)\n",
n, min, shadow_min);
end
if ( max !== shadow_max ) begin
n_err_max++;
if ( n_err_max < 5 )
$write("Error n=%0d max %d != %d (correct)\n",
n, max, shadow_max);
end
end
testbench.t_errs += n_err_min + n_err_max;
done = 1;
$write("Done with n=%0d, tests, %0d min %0d max errors found.\n",
n, n_err_min, n_err_max );
end
endmodule
cadence