////////////////////////////////////////////////////////////////////////////////
///
/// Template for LSU EE 4702-1 Spring 2001 Homework 2
///

 /// Name:


 /// Instructions:
  //
  // Copy this to a file named hw02sol.v to directory ~/hw in your
  // class account. (~ is your home directory.)  Use this
  // file for your solution.  Your entire solution should be in
  // this file.
  //
  // Do not rename the modules in this file and be sure to use the
  // directory and filename given above.

  // Assignment: http://www.ee.lsu.edu/v/2001/hw02.pdf

////////////////////////////////////////////////////////////////////////////////


module priority_encoder_8_b(grant,request);
   input request;  // 8 bits
   output grant;   // 8 bits


endmodule


module priority_encoder_1_es(grant,found_out,request,found_in);
   output grant, found_out;
   input  request, found_in;

   // Don't forget the delays.
   
endmodule

module priority_encoder_8_es(grant, request);
   input request;  // 8 bits
   output grant;   // 8 bits

   // Must instantiate priority_encoder_1_es directly or through
   // other modules (such as priority_encoder_4_es).

endmodule

module tests_pe_8();
   wire done, ok_b, ok_es;
   reg  start;

   // Run testbench 10 times.  Does not verify correct outputs.
   // This module is for your own use, it can be used as is, modified,
   // ignored, etc.
   
   test_pe_8 tpe8(done, ok_b, ok_es, start);

   initial begin

      repeat( 10 ) begin
         start = 1;
         wait( done === 0 );
         // Wait from 0 to 3 cycles, randomly chosen.
         #( $random & 3 );  
         start = 0;
         wait( done === 1 );
         // Wait from 0 to 3 cycles, randomly chosen.
         #( $random & 3 );  
      end
   end
   
endmodule

module test_pe_8(done, okay_b, okay_es, start);
   // All inputs and outputs are 1 bit.
   output done, okay_b, okay_es;  
   input  start;

   // Must run tests each time start is properly set to 1, which
   // can be many times per simulation run.


endmodule