```
// Practice problems for LSU EE 4702 Spring 2000 Final Exam

////////////////////////////////////////////////////////////////////////////////
//
// Problem 1
//

// Show the values of x in the simulation of the module below.

module waits();

wire a,b;
reg [1:0] count;
reg       [7:0] x;
assign    {b,a} = count;

always #2 count = count + 1;

initial begin
count = 0;
x = 0;
wait( a );
x = 1;
wait( a & b );
x = 2;
@( b );
x = 3;
wait( a );
x = 4;
wait( a | b );
x = 5;
@( a );
x = 6;
@( a or b );
x = 7;
#1;
\$stop;
end

endmodule // waits

// Solution:

// Follow:  http://www.ee.lsu.edu/v/2000/feprac.pdf
//  The solution is on the BOTTOM of the page, so scroll down.

////////////////////////////////////////////////////////////////////////////////
//
// Problem 2
//

// The shifter below shifts 8-bit quantities by two bits.

// Re-write it using parameters so that it can shift width-bit
// quantities by amount bits.

// Instantiate a 16-bit wide, 4-bit shift version of the module.

module shifter(x,a,shift);
input a, shift;
output x;

wire       shift;
wire [7:0] a;
wire [7:0] x = shift ? a << 2 : a;

endmodule // shifter

module shifterp(x,a,shift);
input a, shift;
output x;

parameter width = 8;
parameter amount = 2;

wire       shift;
wire [width-1:0] a;
wire [width-1:0] x = shift ? a << amount : a;

endmodule // shifter

// Solution

module use_shifter(x,a,s);
input a, s;
output x;
wire [15:0] a;
wire        s;
wire [15:0] x;

shifterp #(16,4) shifter1(x,a,s);

endmodule // use_shifter

////////////////////////////////////////////////////////////////////////////////
//
// Problem 3
//

// What do the synthesis directives used below do?  What is their
// benefit?

module esm();

parameter /* exemplar enum stype */ st_reset = 0,
st_one = 1, st_two = 2, st_three = 3, st_four = 4;

reg [3:0] /* exemplar enum stype */ state, next_state;

// More code below.

endmodule // esm

////////////////////////////////////////////////////////////////////////////////
//
// Problem 4
//

// Re-write the module below so that it uses a task instead of a function
// to access the array.

reg [31:0] array_2d [1023:0];

input [4:0] x, y;

reg [4:0]     d1, d2;
reg [31:0]    data;

initial begin

d1 = 3;  d2 = 7;

end

endmodule

// Solution

reg [31:0] array_2d [1023:0];

input [4:0] x, y;
output [31:0] d;

d = array_2d[{x,y}];

reg [4:0]     d1, d2;
reg [31:0]    data;

initial begin

d1 = 3;  d2 = 7;

end

////////////////////////////////////////////////////////////////////////////////
//
// Problem 5
//

// What's the difference, if any, between the two case statements below.
// If there is a difference, under what circumstances simulation differ?

module casexz(a);
input a;
wire a;

initial
case ( a )
1'b0:foo;
1'b1:bar;
1'bx:foobar;
endcase // case( a )

initial
casex ( a )
1'b0:foo;
1'b1:bar;
1'bx:foobar;
endcase // case( a )

endmodule // casexz

// Solution:

// Case looks for an exact match, so foobar is only executed
// if a is 1'bx.

// With casex, the unknown value will match anything, so foobar
// is executed if a is 1'bx or 1'bz.

```