EE 4702: Synthesis of Digital Systems
Fall 2002 - Call Number: 1823
- Title:
EE 4702: Synthesis of Digital Systems
- Call No.:
1823
- Professor:
J. Ramanujam, 345 EE Bldg., 578-5628 (Email: jxr@ece.lsu.edu)
- Office Hours:
MWF 8:50 - 10:30
- Time:
11:40 - 12:30 MWF, 145 EE Building
- Grader:
To Be Decided.
- Textbook:
Synthesis and Optimization of Digital Circuits,
Giovanni De Micheli, McGraw-Hill, 1994.
- References:
-
- High-Level Synthesis: Introduction to Chip and System Design,
D. Gajski, N. Dutt, A. Wu and S. Lin, Kluwer, 1992.
- Logic Synthesis,
S. Devadas, A. Ghosh, and K. Keutzer, McGraw-Hill, 1992.
- Introduction to Algorithms,
T. Cormen, C. Leiserson, R. Rivest, MIT Press, 1990.
- Prerequisites:
CSC 3102 and credit/registration in EE 3755. Background in VLSI
or compilers not needed.
The course deals with synthesis and optimization of large scale
digital
systems primarily at the architectural and logic levels. We will also
take a look at processors and compilers for embedded systems.
System-level (hardware and software) design issues will also be discussed.
A new topic that we will discuss this time is FPGA synthesis.
This course covers topics in an important emerging area in digital design.
- Introduction: digital synthesis, application-specific ICs.
- Background in areas such as graph algorithms, combinatorial
optimization, etc.
- Brief overview of hardware description languages: Verilog, VHDL.
- Compiler/software optimization: program analysis and transformations.
- High-level synthesis of data-flow and control units from architectutal specifications:
- clock selection; module selection; resource allocation
- operation scheduling and register binding
- register and memory synthesis
- power optimizations
- design space exploration
- System-level synthesis; hardware-software co-design; FPGA synthesis.
- Embedded systems: power, performance, cost
- Homeworks and Programs (20%)
- Presentation/Project/Report (10%)
- 2 tests (20% each)
- Final (30%)