/// LSU EE 4720 -- Spring 2002 -- Computer Architecture // /// MIPS Implementation Examples // Time-stamp: <19 March 2002, 18:50:15 CST, koppel@sol> // The links below are to Verilog descriptions of the MIPS implementations // described in class. // This page is currently under constructions. At some point // instructions for running the code will be provided. // Running these modules requires: // // A Verilog simulator. (Modelsim works). // // One of the MIPS modules below. // The testbench (also below). // A perlscript to format the pipeline execution diagrams. // The memory modules. // Input programs. (For now, included as Verilog, prepared using // a modified version of spim.) // // Access to the required inputs and detailed instructions will // be provided at some later time. /// Pipelined, Un-Bypassed, No Floating Point // http://www.ece.lsu.edu/ee4720/v/mipspipe.html /// Pipelined, Bypassed, No Floating Point // http://www.ece.lsu.edu/ee4720/v/mipspipeby.html /// Sample Output for program http://www.ece.lsu.edu/ee4720/v/uc.html // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 // 3: la $t0, str IF ID EX ME WB // ori $8, $1, 0 [str] IF ID EX ME WB // 5: lbu $t1, 0($t0) IF ID EX ME WB IF ID EX ME WB // 6: addi $t0, $t0, 0 IF ID EX ME WB IF ID EX ME WB // 7: beq $t1, $0, DON IF ID -> EX ME WB IF ID -> EX ME WB // 8: slti $t2, $t1, 9 IF -> ID EX ME WB IF -> ID EX ME // 9: bne $t2, $0 LOOP IF ID ----> EX ME WB IF ID -> // 10: slti $t2, $t1, IF ----> ID EX ME WB IF -> // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 /// Pipelined, Bypassed, Floating Point //http://www.ece.lsu.edu/ee4720/v/mipspipefp.html /// Output excerpt for program http://www.ece.lsu.edu/ee4720/v/fptest.html // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 // 9: la $t1, OUR_FLOA IF ID EX ME WB // 10: lwc1 $f3, 0($t1 IF ID EX ME WB // 11: lwc1 $f1, 4($t1 IF ID EX ME WB // 12: mul.s $f6, $f3, IF ID -> M1 M2 M3 M4 M5 M6 WB // 13: add.s $f2, $f3, IF -> ID A1 A2 A3 A4 WB // 14: lwc1 $f2, 0($t1 IF ID EX ME WB // 15: sub.s $f3, $f6, IF ID -------> A1 A2 A3 A4 WB // 16: add $7, $2, $3 IF -------> ID EX ME WB // 17: sub $4, $7, $5 IF ID -> EX ME WB // 18: add.s $f6, $f2, IF -> ID A1 A2 A3 // 19: and $6, $7, $8 IF ID EX ME // 20: xor $9, $4, $1 IF ID -> // 21: nop IF -> // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 /// Dynamically Scheduled // So far, no memory and floating point. //http://www.ece.lsu.edu/ee4720/v/mipspipeds.html /// Output excerpt for program http://www.ece.lsu.edu/ee4720/v/dstest.html // Note: Squashes not shown (yet). // Bypassing not yet implemented so dependent instructions must wait. // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 // 6: add $7, $2, $3 IF ID Q RR EX WB C // 7: bne $12, $13, D IF ID Q RR EX WB C // 8: sub $4, $7, $5 IF ID Q RR EX WB C // 12: addi $2, $0, 10 IF ID Q RR EX WB C // 14: andi $4, $9, 1 IF ID Q RR EX WB C // IF ID Q RR EX WB // 15: bne $4, $0, SKI IF ID Q RR EX WB C // IF ID Q // 16: add $3, $3, $2 IF ID Q RR EX WB C // IF ID Q // 17: sll $10, $9, 1 IF ID // 18: srl $5, $10, 31 IF // 22: bne $2, $0, LOO IF ID Q RR EX WB // IF ID Q // 23: addi $2, $2, -1 IF ID Q RR EX // IF ID Q // 24: or $20, $21, IF ID Q // 25: syscall IF ID* // 26: nop IF // Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 /// Testbench // Used for all of the modules above. //http://www.ece.lsu.edu/ee4720/v/mipspipetb.html