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fr-1 Fall 1999 Final Exam Review *
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When / Where
Alternate: Tuesday, 7 December, 15:00-17:00 (3 pm to 5 pm) CST, Room EE 117.
Original: Monday, 6 December, 10:00-12:00 CST, Room EE 145 (Here)
Conditions
Open Book, Open Notes
Bring any amount of books, notes, and other material : : :
: : :as long as they can be carried 100 meters without stopping.
No communication devices.
Format
Two or three problems.
One set of short answers.
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Resources
Study recommendations: href = "http://www.ee.lsu.edu/ee4720/exam.html"
Solved tests and homework:. href = "http://www.ee.lsu.edu/ee4720/prev.html"
Study Recommendations
Solve_ Old Problems
Memorizing solutions is not the same as solving.
Following and understanding solutions is not the same as solving.
Use the solutions for brief hints and to check your own solutions.
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Topics
Introductory Material
ISA v. Implementation.
Technological Factors: Transistor speed and quantity, memory speed and size.
Different factors influencing ISA and implementation.
Design principles: Amdahl's law, locality.
CPU Performance Equation
Benchmark types.
Instruction Set Design
Data Types: What to include, what to leave out.
Basic integer and floating point
Packed types: BCD, integer, saturating integer.
Size choices.
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Memory and Register Organization: Why ss 32 registers?
Stack and accumulator architectures.
Memory/Memory, Register/Memory.
Addressing Modes: What they do, which ones to include.
Register, Immediate, Direct, Register Deferred (Register Indirect), Displacement, In-
dexed, Memory Indirect, Autoincrement, Autodecrement, Scaled.
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Control Transfer Instructions: Types, when to use.
Branch, Jump, Jump & Link, Call, Return
Format of displacements in instruction.
Specification of condition: condition code registers, integer registers, loop counter.
Delayed and predicated instructions; prediction hints.
Instruction Coding.
Fixed-length, variable-length, and bundled instructions.
Splitting of opcode field (as in DLX type-R instructions).
ISA Classifications: RISC, CISC, VLIW, Stack, Accumulator
Synthetic Instructions
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DLX
Classification: RISC
Goals: ISA should allow simple, high-speed implementation.
Instruction types.
Know how to read and write DLX programs.
Chapter-3 (Static Scheduled) DLX Implementations
Unpipelined Implementation
Pipelined Implementations
Basic (3-cycle branch delay).
One-cycle branch delay.
Bypassed.
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Hazard Definitions
For a Given Pipelined Implementations
Show pipeline execution diagrams.
Show register contents at any cycle.
Determine control hardware.
Determine CPI.
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Interrupts, Exceptions, Traps
Difference between interrupt, exception, trap.
Causes of exceptions, role of handler.
Privileged Mode.
Pipeline activity leading to execution of handler.
Vectored traps (using trap table).
Precise exceptions, achieving with floating-point operations.
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Long Latency Operations
Types of operations. (Floating point and maybe load.)
Degree of pipelining: Initiation interval, latency.
Detecting functional unit structural hazards.
Detecting WB structural hazards: reservation register.
Detecting and handling RAW hazards: ID-stage v. pre-WB stall.
Handling WAW hazards.
Instruction-Level Parallelism
Definition, analysis.
Dependency definitions.
Basic block definition.
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Loop Unrolling
Dynamic Scheduling
Reservation stations.
Register Renaming
How renaming allows out-of-order execution.
Where registers get renamed.
Role of register map.
Register Names:
Reorder buffer entry number.
Reservation station number.
Physical register number.
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Reorder Buffer
Normal Use
Issue: placement of instructions in reorder buffer.
Completion: updating reorder buffer entry
Commitment (retirement): removal from reorder buffer entry.
Recovery
Goal: Undo execution starting at some instruction.
Reasons: exception, branch misprediction.
Steps when register map backed up.
Steps when register map not backed up.
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Load/Store Unit
Store/load ordering rules.
Load/store bypassing.
Multiple Issue
Superscalar
Duplication of Resources.
For n instructions / cylce: Fetch, decode, rename, writeback, commit.
For < n instructions: load/store, floating-point units.
Added Complexity
Instruction fetch inefficiency.
Rules for fetching a new group.
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VLIW
Difference with superscalar: instruction bundling.
Dependence information in bundles.
Branch Prediction
One-level branch prediction.
Two-level (gshare, gselect) branch-prediction.
Branch target prediction.
Branch folding.
Memory
Connection of memory devices.
Set-Associative Caches.
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| David M. Koppelman - koppel@ee.lsu.edu | Modified 3 Dec 1999 11:41 (17:41 UTC) |