# EE 4720 Computer Architecture - HW 6 Solution

### Problem 1

An illustritive program and its execution is shown for each entry in the table. The "Lat" row shows the cycles counted in the latency. Note that the floating-point units use their own memory and writeback stages, called MF and WF, respectively.

#### Program for Figure 4.2 Entry 1

``` addd f0, f2, f4
addd f6, f0, f2
```
Timing:
```Time 0   1   2   3   4   5   6   7   8   9   10  11
Lat              1   2   3
addd IF  ID  A1  A2  A3  A4  MF  WF
addd     IF  ID              A1  A2  A3  A4  MF  WF
```

#### Program for Figure 4.2 Entry 2

``` addd f0, f2, f4
sd 0(r1), f0
```
Timing:
```Time 0   1   2   3   4   5   6   7   8   9   10  11
Lat                  1   2
addd IF  ID  A1  A2  A3  A4  MF  WF
sd       IF  ID  EX          MEM WB
```
Note that store stalls in the EX stage.

#### Program for Figure 4.2 Entry 3

``` ld   f2, 0(r1)
addd f0, f2, f4
```
Timing:
```Time 0   1   2   3   4   5   6   7   8   9   10  11
Lat              1
ld   IF  ID  EX  MEM WB
addd     IF  ID      A1  A2  A3  A4  MF  WF
```

#### Program for Figure 4.2 Entry 4

``` ld   f2, 0(r1)
addd f0, f2, f4
```
Timing:
```Time 0   1   2   3   4   5   6   7   8   9   10  11
Lat
ld   IF  ID  EX  MEM WB
sd       IF  ID  EX  MEM WB
```

### Problem 2

Note: solution based on simplified R4000 issue rules, so timing will not match a real R4000.

```Time 0   1   2   3   4   5   6   7   8   9   10  11  12  13  14  15  16  17  18
ld   IF  IS  RF  EX  DF  DS  TC  WB
neg      IF  IS  RF          U   S   DF  DS  TC  WB
add          IF  IS          RF      U   S+A A+R R+S DF  DS  TC  WB
cgt              IF          IS      RF      U   A   R   DF  DS  TC  WB
add                          IF      IS      RF  U   S+A A+R R+S DF  DS  TC  WB
```

 David M. Koppelman - koppel@ee.lsu.edu Modified 18 Apr 1997 15:09 (20:09 UTC)