# EE 4720 Computer Architecture - HW 4 Solution

### Problem 1

In the timing diagrams below the active PM mask bit is indicated for each cycle. In the solution to homework 3, instructions are nullified (replaced with NOPs) in the EX stage; the segments used by nullified instructions are surrounded by X's. Note that the mask bit is checked in the EX stage and that because of pipeline stalls, mask bits become misaligned with instructions. For example, in the execution below, because the SUB instruction stalls it "misses" its zero.

With R4 = 0:

```Time:0   1   2   3   4   5   6   7   8   9   10
Mask:		 0   1	 0   1	 1   1	 1   1
PM   IF  ID  EX  MEM WB
ADD	 IF  ID  XEX XMX XWX
LW	     IF  ID  EX  MEM WB
SUB		 IF  ID      EX  MEM WB
```
Below, the SUB instruction executes normally (albeit with a stall) because the NOP was inserted in the EX stage while SUB was stalled in ID.

With R4 = 1

```Time:0   1   2   3   4   5   6   7   8   9   10
Mask:		 1   0	 1   1	 1   1	 1   1
PM   IF  ID  EX  MEM WB
ADD	 IF  ID  EX  MEM WB
LW	     IF  ID  XEX XMX XWX
SUB		 IF  ID      EX  MEM WB
```
Note that, if the controller doesn't know that LW will be nullified, it will have to stall SUB to avoid the possible RAW hazard. (The stall is unnecessary in this case.)

For R4 = 1, R5 = 0, Mask = 00010011

```Time: 0   1   2   3   4   5   6   7   8   9   10
Mask:	          1   1	  0   0	  1   0	  0   0
PM    IF  ID  EX  MEM WB
ADD	  IF  ID  EX  MEM WB  IF  ID  XEX XMX XWX
BEQZ	      IF  ID  EX  MEM WB  IF  ID  XEX XMX XWX
SUB		  IF  ID	      IF  ID  XEX XMX XWX
```
For R4 = 1, R5 = 1, Mask = 00010011
```Time: 0   1   2   3   4   5   6   7   8   9   10
Mask:	          1   1	  0   0	  1   0	  0   0
PM    IF  ID  EX  MEM WB
ADD	  IF  ID  EX  MEM WB
BEQZ	      IF  ID  EX  MEM WB
SUB		  IF  ID  XEX XMX XWX
```
For R4 = 0, R5 = 1 or R5 = 0, Mask = 11111100
```Time: 0   1   2   3   4   5   6   7   8   9   10
Mask:	          0   0	  1   1	  1   1	  1   1
PM    IF  ID  EX  MEM WB
ADD	  IF  ID  XEX XMX XWX
BEQZ	      IF  ID  XEX XMX XWX
SUB		  IF  ID  EX  MEM WB
```

### Problem 2

Use a shift register in which all all bits are available, not just the bit at the end of the register. And these bits together, call the result DONE. DONE indicates that the current and next seven instructions will execute. Generate a second signal, PM_ILL, by detecting an LW or CTI instruction opcode in the EX stage. Then PM_VIOL is the and of PM_ILL and NOT DONE. The exception can easily be made precise since it is detected while the the faulting instruction is in the EX stage, and so the following instructions can easily be abandoned since they are only in the IF and ID segments.

These changes are shown below; blue indicates changes for homework 3 and red indicates changes for this problem. Note the exaggerated inversion bubble at the shift register shift input.