Configuring an Altera FPGA with a Basic Stamp


You may have been wondering to yourself "Can I configure and FPGA with a Basic Stamp?" Well, you are in luck. Not only can it be done, it is as useless as you had imagined. The information below comes from a robotics project. A board was constructed with a BS2P40 primary CPU and an Altera FLEX10K10 FPGA to handle any real-time activities.

Connections

You will need to wire the basic stamp to the FPGA (a flex10k part in my case) using the following lines: DCLK,DATA0, N_CONFIG,CONF_DONE, and N_STATUS per the instructions located in the Altera Configuration Handbook, chapter 8 (document CF51006-2.0).

You will also need the configuration data! I store this in an onboard I2C serial EEPROM. The configuration data for the Flex10k10 part is slightly under 15kB so it fits nicely in a 16kB EEPROM. You will need to use the Quartus tool to convert a *.sof file into a raw binary file *.rbf. Then this must be downloaded from the computer to the Basic Stamp and stored in the EEPROM.

Here are two programs, BS2P code to receive and store the data from a Mac, and a Mac OSX program that will send a binary file to the BS2 using a USB/serial adapter. The length of the file is stored in the first two bytes of EEPROM. I make no warranties here. This is strictly a hack for amusement purposes.

BS2P_EEPROM_loader.bsp

BS2Load.zip

Operation

The configuration scheme is fairly straightforward. The FPGA is reset and data is clocked in serially until all data is sent. The FPGA is then configured. It takes 7 seconds to accomplish. I had one nagging glitch. Apparently the switch to I2C activity on the BS2P glitches the entire output port. This was resetting the FPGA and wreaking havoc every time I fetched new configuration data. The problem was solved by adding a small capacitor to the N_STATUS pin. To be honest I never really saw the glitch on the digital scope, but the symptoms were all there.

The following file will configure the FPGA on power up by running a program in slot 0. Following configuration, the program in slot 1 is executed.

fpga_bootload_light.bsp