EE3755
practice final 2003.

For
Computer Arithmetic, Just study the last 2 problems of this practice final.

problem
1.  Write MIPS machine code for the
following instructions.

LOOP:

0x400000    add r1, r2, r3

beq r0,r0,LOOP

Hint :

opcode for add is 0 and  fun field value is  20.

opcode for beq is 4.

problem
2. write the  register values after executing following
instructions.

0x1000:

0x1000

addi r1, r0, 3;

R1=

R2=

R3=

R4=

R31=

addi r2, r0, 5;

R1=

R2=

R3=

R4=

R31=

sub  r3, r1, r2;

R1=

R2=

R3=

R4=

R31=

sub  r3, r1, r2;

R1=

R2=

R3=

R4=

R31=

bne  r3, r0, loop;

R1=

R2=

R3=

R4=

R31=

ori    r1, r2, 20;

R1=

R2=

R3=

R4=

R31=

addi  r6, r0,
0x2000;

R1=

R2=

R3=

R4=

R31=

jalr r6;

R1=

R2=

R3=

R4=

R31=

problem
3. Write MIPS program to print  “EE3755”;

hint)
data, text, global, system call,

problem
4. What is wrong with following instructions.

addi r1,
r2,0x123456789;

problem
5. compile the c code to the MISPs
code.

if(a > b) d = d >>1; else d = d
<< 1;

register usage  a, $8; b, $9; d , $10;

problem
6. give examples about DCE, CSE and loop unrolling.

problem
7. Write a MIPS code for swap.

problem
8. Draw  the
datapath so SW instruction can be done.

Problem 9.   Compute execution time and CPI.

The Finite
State Diagram has 10 state.

Clock cycle
is 2ns.

state 0
takes 1.5 ns.

state 2-9
takes 2 ns.

Instruction
mix is this following:

Memory access(LW and SW) is each 10%.

R-type is
70%.

BEQ is 10
%.

J is 10 %.

a)Compute
single cycle CPI.

b)Compute
multi cycle CPI.

c)Designers
of new machine found out

new
technology with  1 ns clock cycle
and each state takes only

0.9 ns
except state 9 which takes 1.8 ns.

c-1) Compute
single cycle CPI

c-2)
Compute multi cycle CPI.

c-3)
Designers found out  a method to
divide the state 9 into 2 states(
the new 2 stake, state 9-1 and state 9-2) .

state 9-1 takes 1.1 ns.

state 9-2
takes 1.2 ns.

Is the performance is better or worse?

(Why ).

Problem 10.    Fill the table for SRC2
column.

(you will be given the datapath
diagram for multicycle control)

Problem 11:
Consider the multiplicative division technique for computing Q=A/B. Here A, B
are positive fractions with B being normalized. Also A<B
so that Q be a fraction. If the hardware allows precision of 16
fractional bits, what is the maximum number of iterations that need to be
performed before the technique stops?

Justify your
answer.  What is the overall factor
F in this case?

Answer : The maximum number of iterations to be
performed (before the techniques stops) is four, since B is normalized fraction,
then ½ ≤ B < 1 and therefore B=1-δ where 0 < δ
≤ ½ . The factors involved are F1=1+ δ, F2=1+
δ2, F3=1+ δ4, F4=1+
δ8.

1st
iteration gives B1= B×F1 =(1-
δ)(1+ δ)=1- δ2

2nd
iteration gives B2= B1×F2 =(1- δ2)(1+ δ2)=1- δ4

3rd iteration
gives B3= B2×F3 =(1-
δ4)(1+ δ4)=1- δ8

4th iteration
gives B4= B3×F4 =(1-
δ8)(1+ δ8)=1- δ16

Since 0
< δ ≤ ½ then 0 < δ16 ≤ ½16
and thus B4= 1- δ16 ≥ 1 - ½16 =

(216-1)
/ 216=.111……..111

16 ones

Therefore,
after at most four iterations the technique stops. The overall factor F is F= F1×F2×F3×F4=(1+ δ)( 1+ δ2)( 1+ δ4)
)( 1+ δ8), and Q≈A×F.

Problem12: Consider the following two binary unsigned
numbers: A=a4a3a2a1a0 and
B= b2b1b0 where a4 and b2
are the most significant bits of A and B while a0 and b0
their least significant bits consider the multiplication P=A ×B.

a)     Show the
diagram of the 5-by-3 unsigned array multiplier.

If the
propagation delay through a 2-input AND gate is DAND and the
propagation delay through a Full Adder is DFA, compute the
propagation delay through the 5-by-3 unsigned array multiplier.

b)     What is the
cost of the above 5-by-3 multiplier in terms of number of AND gates and number
of full adders?

Answer :

a>

b>Delay=DAND + (2+4) DFA = DAND
+ 6DFA

c> Cost=15 AND gates + 12 Full Adders