////////////////////////////////////////////////////////////////////////////////
///
/// Template for LSU EE 3755 Fall 2003 Verilog Homework 2
///
 
 
 
 /// Instructions:
 //
 // Copy this to a file named hw02.v to directory ~/hw in your
 // class account. (~ is your home directory.) Use this
 // file for your solution. Your entire solution should be in
 // this file.
 //
 // Do not rename the modules in this file and be sure to use the
 // directory and filename given above.
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
/// Problem 0
///
 
module hello_it_is_me();
 
 $display(“My account, My name\n”); //just type your account and name
 
 
endmodule
 
 
////////////////////////////////////////////////////////////////////////////////
/// Problem 1
///
 
module find_character_c(character_count,v,character_in);
 input [31:0] v;
 input [7:0] character_in;
 output [1:0] character_count;
 
 // Solution goes here.
 
endmodule
 
 
////////////////////////////////////////////////////////////////////////////////
/// Problem 2
///
module find_character_s(character_count,character_bit_in,character_in,clk,start);
 input character_bit_in;
 input [7:0] character_in;
 input clk;
 input start;
 output [4:0] character_count;
 
 //do something here.
aways @( posedge clk)
 begin
 if(start)
 begin
 //do something here
 end
 
 // Solution goes here.
 
 
 
 
endmodule