/// LSU EE 3755 -- Fall 2001 -- Computer Organization
//
/// Strawman MIPS, As Seen in Class [tm]
//
// Time-stamp: <14 November 2001, 16:20:22 CST, koppel@sol>
//
// This file contains the Verilog code for the strawman MIPS
// implementation being written in class.  It is probably not complete
// and might not be working, even considering its incomplete form.
// Completed code will also be posted.

`define MIPS_PROG "prog1.v"


`define MEMBASE 'h400000
`define DATABASE 'h10010000
`define TEXTSIZE 'h100
`define MEMSIZE 'h200
`define MEMRANGE `MEMBASE:`MEMBASE+`MEMSIZE-1
`define A(addr) ((addr)-`DATABASE+`MEMBASE+`TEXTSIZE)
`define MEM(addr) mem[((addr)-`DATABASE+`MEMBASE+`TEXTSIZE)]

module proc(exc,clk);
   input clk;
   output exc;
   reg    exc;

   reg [31:0] gpr [0:31];
   reg [7:0]  mem ['h400000:'h400100];

   reg [31:0] pc, npc;
   reg [31:0] ir;

   reg [4:0]  rs, rt, rd, sa;
   reg [5:0]  opcode, func;
   integer    i;

   // Values for funct field.
   parameter  f_sll = 6'h0;
   parameter  f_srl = 6'h2;
   parameter  f_add = 6'h20;
   parameter  f_sub = 6'h22;
   parameter  f_or  = 6'h25;

   // Values for opcode field.
   parameter  o_rfmt = 6'h0;
   parameter  o_j    = 6'h2;
   parameter  o_beq  = 6'h4;
   parameter  o_bne  = 6'h5;
   parameter  o_addi = 6'h8;
   parameter  o_slti = 6'ha;
   parameter  o_andi = 6'hc;
   parameter  o_ori  = 6'hd;
   parameter  o_lui  = 6'hf;
   parameter  o_lw   = 6'h23;
   parameter  o_lbu  = 6'h24;
   parameter  o_sw   = 6'h2b;
   parameter  o_sb   = 6'h28;

   initial begin exc = 0; i = 0; end

   always @( posedge clk ) begin

      ir = {mem[pc],mem[pc+1],mem[pc+2],mem[pc+3]};

      {opcode,rs,rt,rd,sa,func} = ir;

      case( opcode )

        o_rfmt:

          case ( func )

            f_add: gpr[rd] = gpr[rs] + gpr[rt];
            f_sub: gpr[rd] = gpr[rs] - gpr[rt];
            default: exc = 1;

          endcase

        default: exc = 1;

      endcase

      i = i + 1;
      if( i==3 ) exc = 1;

      pc = pc + 4;

   end

endmodule

// Include the testbench.

`include "mipsi1tb.v"