/// LSU EE 3755 -- Fall 2001 -- Computer Organization // /// Testbench for Strawman MIPS // // Time-stamp: <14 November 2001, 16:31:27 CST, koppel@sol> // exemplar translate_off module test_proc(); wire exception; reg clk; proc p1(exception,clk); reg [31:0] gpr_shadow [0:31]; reg [319:0] isource[`MEMBASE>>2:((`MEMBASE+`MEMSIZE)>>2)-1]; reg [31:0] regname [0:31]; integer i, reg_old, reg_new; always begin clk = 0; #10; clk = 1; #10; end task initmem; input [31:0] addr; input [31:0] text; input [319:0] source; begin if( addr & 3 ) begin $display("Unaligned instruction address, 0x%h",addr); $stop; end if( addr < `MEMBASE || addr >= `MEMBASE + `TEXTSIZE ) begin $display("Address 0x%h out of range.",addr); $stop; end {p1.mem[addr],p1.mem[addr+1],p1.mem[addr+2],p1.mem[addr+3]} = text; while( source[319:312] === 8'b0 ) source = {source[311:0]," "}; isource[addr>>2] = source; end endtask task initdmem; input [31:0] addr; input [31:0] word; reg [31:0] daddr; begin if( addr & 3 ) begin $display("Unaligned data address, 0x%h",addr); $stop; end if( addr < `DATABASE || `A(addr) >= `MEMBASE + `MEMSIZE ) begin $display("Data address 0x%h out of range.",addr); $stop; end daddr = `A(addr); {p1.mem[daddr],p1.mem[daddr+1],p1.mem[daddr+2],p1.mem[daddr+3]} = word; end endtask integer rno; task initregs; input [31:0] name; input [3:0] cnt; integer i; for(i=0; i