Reconfigurable Architectures Workshop (RAW 2009)
Advance Program
Monday May 25
9:00-9:05 - Chair's Welcome
9:05-10:00 – RAW Keynote - Frank Vahid
10:00-11:00 - Break and Poster Session 1
11:00-12:15 - Session 1 (3 papers - 25 min/each)
12:15-13:45 - Lunch
13:45-15:00 - Session 2 (3 papers - 25 min/each)
15:00-15:30 - Break
15:30-17:10 - Session 3 (4 papers - 25 min/each)
Tuesday May 26
8:00-9:30 - IPDPS Keynote (Wen-Mei Hwu)
9:30-10:30 - Break and Poster Session 2
10:30-11:30 – RAW Keynote - Rainer Hartenstein
11:30-12:45 - Session 4 (3 papers - 25 min/each)
12:45-13:45 - Lunch
13:45-15:00 - Session 5 (3 papers - 25 min/each)
15:00-15:30 - Break
15:30-17:10 - Session 6 (4 papers - 25 min/each)
17:10-17:15 - Closing remarks
Session 1: Architecture
Evaluation of a Multicore Reconfigurable Architecture with Variable Core Size
Tuan Vu, Hideharu Amano and Hiroki Matsutani
ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores
Heiner Giefers and Marco Platzner
Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements
Tung Hoang
Session 2: Digital Signal Processing
Energy Benefits of Reconfigurable Hardware for use in Underwater Sensor Nets
Bridget Benson and Ali Irturk and Ryan Kastner
A Multiprocessor Self-Reconfigurable JPEG2000 Encoder
Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi and Donatella Sciuto
Reconfigurable Accelerator for WFS-Based 3D-Audio
Dimitris Theodoropoulos, Georgi Kuzmanov and Georgi Gaydadjiev
Session 3: Applications
A MicroBlaze Specific Co-Processor for Real-Time Hyperelliptic Curve Cryptography on Xilinx FPGAs
Alexander Klimm and Oliver Sander and Juergen Becker
Implementing Protein Seed-Based Comparison Algorithm on the SGI RASC-100 Platform
Van-Hoa Nguyen
Hardware Accelerated Montecarlo Financial Simulation over Low Cost FPGA Cluster
Javier Castillo, Jose Bosque, Emilio Castillo, José Ignacio Martinez and Pablo Huerta
High Performance True Random Number Generator Based on FPGA Block RAMs
Tamas Gyorfi, Octavian Augustin Cret and Alin Suciu
Session 4: Network on chip
Design and implementation of the Quarc Network-on-Chip
Mahmoud Moadeli, Partha Maji and Wim Vanderbauwhede
A Novel Hardwired NOC Framework with Unified Configuration and Functional Architectures
Muhammad Aqeel Wahlah and Kees Goossens
A Low Cost and Adaptable Routing Network for Reconfigurable Systems
Ricardo Ferreira, Marcone Laure, Thiago Lo, Antonio Carlos Beck and Luigi Carro
Session 5: Runtime reconfiguration
Runtime Decision of Hardware or Software Execution On A Heterogeneous Reconfigurable Platform
Vlad Sima and Koen Bertels
Impact of Run-Time Reconfiguration on Design and Speed - A Case Study Based on a Grid of Run-Time Reconfigurable Modules inside a FPGA
Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm and Heiko Schick
System Level Runtime Mapping Exploration of Reconfigurable Architectures
Kamana Sigdel, Mark Thompson, Andy Pimente, Koen Bertels and Carlo Galuzzi
Session 6: Design Tools
3D FPGA Resource Management and Fragmentation Metric for HW Multitasking
Jose Antonio Valero, Julio Septien, Hortensia Mecha and Daniel Mozos
RDMS: A Hardware Task Scheduling Algorithm for Reconfigurable Computing
Miaoqing Huang, Harald Simmler, Serres Olivier and Tarek El-Ghazawi
Flexible Pipelining Design for Recursive Variable Expansion
Zubair Nawaz, Thomas Marconi, Todor Stefanov and Koen Bertels
Generation of Synthetic Floating-Point Benchmark Circuits
Chun Pong Chau, Philip Leong, Man Ho Ho, Peter Zipf and Manfred Glesner,
Posters Session 1:
The Radio Virtual Machine: A Solution for SDR Portability and Platform Reconfigurability
Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet and Yves Durand
Scheduling Tasks on Reconfigurable Hardware with a List Scheduler
Justin Teller and Fusun Ozguner
Software-Like Debugging Methodology for Reconfigurable Platforms
Loic Lagadec
Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor
Nivesh Rai, Nupur Lodha and Hrishikesh Venkataraman
Achieving Network on Chip Fault Tolerance by Adaptive Remapping
Cristinel Ababei and Rajendra Katti
On The Acceptance Tests of Aperiodic Real-Time Tasks for FPGAs
Hatem El-Boghdadi, Ahmed El-Farag and Samir Shaheen
Poster Session 2 :
High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrholz, Philipp Hartmann and Wolfgang Nebel
Optimized Smith-Waterman Implementation on a FSB-FPGA module using the Intel Accelerator Abstraction Layer
Jeffrey Allred, Jack Coyne, William Lynch, Vincent Natoli, Joel Morrissette and Joseph Grecco
High-Level Synthesis with Coarse Grain Reconfigurable Components
George Economakos and Sotiris Xydis
A Layered Operating System Support For On-Line Management Of Reconfigurable Cores
Marco Santambrogio, Ivan Beretta, Vincenzo Rana and Donatella Sciuto
Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric
Gayatri Mehta, Colin Ihrig, Mustafa Baz and Alex Jones