*********************************** * * * Call For Papers * * * * RAW 2007 * * * * March 26 - 27, 2007 * * * *********************************** Submission deadline extended to October 15, 2006 The 14th Reconfigurable Architectures Workshop (RAW 2007) will be held in March 26 - 27, 2007. RAW 2007 is associated with the 21th Annual International Parallel & Distributed Processing Symposium (IPDPS 2007) and is sponsored by the IEEE Computers Society's Technical Committee on Parallel Processing. RAW 2007 is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. Main Focus of the Workshop: Run-Time Reconfiguration & Adaptive Computing: Architectures, Algorithms, Technologies Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse/multi-grain devices) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2007 aims to provide a forum for creative and productive interaction between all these disciplines. Special Focus: Coarse Grain Reconfiguration RAW 2007 wants to emphasize the importance of coarse grain reconfiguration, including architectures, models, applications, algorithms and tools. We strongly encourage researchers to submit novel results in these areas. Accepted papers will be presented in special sessions. Topics of Interest: Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to: Models & Architectures Theoretical Interconnects & Computational Models RTR Models and Systems RTR Hardware Architectures Optical Interconnect Models Simulation and Prototyping Bounds and Complexity Issues Algorithms & Applications Algorithmic Techniques Mapping Parallel Algorithms Distributed Systems & Networks Fault Tolerance Issues Wireless and Mobile Systems Automotive Applications Infortainment & Multimedia Biology Inspired Applications Technologies & Tools Configurable Systems-on-Chip Energy Efficiency Issues Devices and Circuits Reconfiguration Techniques High Level Design Methods System support Adaptive Runtime Systems Organic Computing Submission Guidelines: Authors should submit and register their paper by October 15, 2006 through the web interface at http://raw.itiv.uni-karlsruhe.de (The web interface will be available after September 1, 2006.) All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 pages of single spaced text, including figures and tables) or, in special cases, may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Authors should make sure that the submission can be viewed using ghostscript and will print on standard letter size paper (8.5" x 11"). IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk. Important Dates: Manuscript due October 25, 2006 Notification of acceptance/rejection December 15, 2006 Organization : Workshop Chair: Mladen Berekovic, IMEC, Belgium berekovic@imec.be Program Chair: Juergen Becker, Universitat Karlsruhe (TH), Germany becker@itiv.uni-karlsruhe.de Steering Chair: Viktor K. Prasanna, University of Southern California, USA prasanna@ganges.usc.edu Publicity Chair (USA): Ramachandran Vaidyanathan, Louisiana State University, USA vaidy@ece.lsu.edu Publicity Chair (Europe, Asia): Reiner Hartenstein, Kaiserslautern University of Technology, Germany reiner@hartenstein.de Program Committee (to be confirmed): Jeffrey Arnold, Adaptive Silicon Inc. Mauricio Ayala , Universidade de Brasilia Helena Krupnova, ST Microelectronics Sergio Bampi, Universidade Federal do Rio Grande Vera Lauer, DaimlerChrysler AG Juergen Becker, Universitaet Karlsruhe (TH) Rudy Lauwereins, IMEC, Leuven Pascal Benoit, LIRMM Philip Leong, Chinese University of Hong Kong Mladen Berekovic, IMEC Marnane Liam, University College Neil Bergmann, University of Queensland Wayne Luk, Imperial College Don Bouldin, University of Tennessee Juergen Luka, DaimlerChrysler AG Elaheh Bozorgzadeh, University of California Patrick Lysaght, Xilinx Gordon Brebner, Xilinx Thomas Buechner, IBM John McHenry, National Security Agency Fabio Campi, Universita di Bologna Martin Middendorf, University of Leipzig Luigi Carro, Universidade Federal do Rio Grande Amar Mukherjee, University of Central Florida Peter Y. K. Cheung, Imperial College, London Koji Nakano, Hiroshima University Andreas Dandalis, Philips Ranjani Parthasarathi, Anna University, Chennai Marco Platzner, Universitat Paderborn Oliver Diessel, University of New South Wales Cameron Patterson, Virginia Tech Adam Donlin, Xilinx Thilo Pionteck, Universitat Lubeck Joachim Pistorius , Altera Pedro C. Diniz, University of Southern California Bernard Pottier, Universite de Bretagne Occidentale Gilbert Edelin, Thales Research & Technology Franz Rammig, Universitat Paderborn Hossam ElGindy, University of New South Wales Ricardo Reis, Universidade Federal do Rio Grande Marco Santambrogio, Politecnico di Milano Manfred Glesner, Darmstadt University of Technology Hartmut Schmeck, Universitat Karlsruhe (TH) Steve Guccione, Cmpware, Inc. Sakir Sezer, Queen's University Gerard Smit, University of Twente Masanori Hariyama, Tohoku University Srinivas Katkoori, Univ of South Florida Reiner Hartenstein, University of Kaiserslautern V. Sridhar, Satyam Computer Services Ltd. Ulrich Heinkel, Lucent Technologies Juergen Teich, Friedrich-Alexander-Universitaet Erlangen Andreas Herkersdorf, Institute for Integrated Systems Lionel Torres, LIRMM, Montpellier Christian Hochberger, Dresden University of Technology Jim Torresen, University of Oslo Thomas Hollstein, Darmstadt University of Technology Jerry L. Trahan, Louisiana State University Ramachandran Vaidyanathan, Louisiana State University Michael Hubner, Universitat Karlsruhe Carlos Valderrama, University Mons Mark Jones, Virginia Tech Milan Vasilko, Bournemouth University Stamatis Vassiliadis, Delft University of Technology Udo Kebschull, Universitat Leipzig Brian Veale, University of Oklahoma Andreas Koch, Technische Universitat Braunschweig Martin Vorbach, PACT Informationstechnologie Rainer Kress, Infineon Technologies Klaus Waldschmidt, Universitat Frankfurt Norbert Wehn, University of Kaiserslautern RAW 2007 Home http://www.ece.lsu.edu/vaidy/raw/