Tuesday, April 5th 2005


8.00 9.30 IPDPS Keynote (Plenary Session)

David Culler
University of California, Berkeley
"Wireless Sensor Networks - Where Parallel
and Distributed Processing meets the Real World"

9.30 10.10 Keynote II

Mike Hutton, Principal Engineer Altera
Altera Corp., USA
"Old and New Challenges in FPGA Architecture Design"

10.10 10.30 Coffee Break

10.30 11.30 Session 8 Processor Based Approaches I

Session Chair: TBD
Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima,
Makoto Ozone, Katsunori Hirase
Digital Systems Development Center, SANYO Electric Co., Ltd
Shinji Kimura
Graduate School of Information, Production and Systems,
Waseda University; Japan
"A Reconfigurable Processor based on ALU array
architecture with limitation on the interconnection"

Brian Veale, John Antonio
School of Computer Science, University of Oklahoma, USA
Monte Tull
School of Electrical and Computer Engineering,
University of Oklahoma, USA
"Configuration Steering for a Reconfigurable
Superscalar Processor"

Toshiyuki Ito, Junji Kitamichi, Kenichi Kuroda
The University of Aizu, Japan
Yuichi Okuyama
NTT Network Innovation Laboratory
"A Master-Slave Adaptive Load Distribution
Processor Model on PCA"

11.30 12.00 Session 9 Poster Session

Session Chair: TBD
See Tuesday Poster Session Schedule
In addition you are invited to take a look at the posters until 6pm.

12.00 13.15 Lunch Break

13.15 13.55 Session 10 Processor Based Approaches II

Session Chair: TBD
Razali Jidin, David Andrews, Wesley Peck, Dan Chirpich,
Kevin Stout, John Gauch, University of Kansas, USA
"Evaluation of the Hybrid Multithreading Programming
Model Using Image Processing Transforms"

Remy Eskinazi, University of Pernambuco - Polithecnic School, Brazil
Paulo Maciel, Manoel Eusebio, Paulo Nascimento,
Abel Guilhermino, Carlos Valderrama, Federal University of Pernambuco, Brazil
"A Timed Petri Net Approach for Pre-Runtime
Scheduling in Partial and Dynamic Reconfigurable Systems"


13.55 14.35 Session 11 Network on Chip

Session Chair: TBD
Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
University of Erlangen-Nuremberg, Germany
"Packet Routing in Dynamically Changing Networks on Chip"
Pascal Wolkotte, Gerard Smit, Gerard Rauwerda, Lodewijk Smit
University of Twente, The Netherlands
"An Energy-Efficient Reconfigurable Circuit
Switched Network-on-Chip"

14.35 15.00 Coffee Break

15.00 16.20 Session 12 Acceleration Application

Session Chair: TBD
Michalis Galanis, Athanassios Milidonis, Costas Goutis,
University of Patras, Greece
Giorgos Theodoridis, Aristotle University, Greece
Dimitrios Soudris, Democritus University of Thrace, Greece
"A Framework for Partitioning Computational Intensive
Applications in Hybrid Reconfigurable Platforms"

Melissa Smith, Jeffery Vetter, Oak Ridge National Laboratory, USA
Xuejun Liang, Jackson State University, USA
David Caliga, SRC Computers, USA
"Accelerating Scientific Applications with the SRC-6E
Reconfigurable Computer: Methodologies and Analysis"

Aravind Dasu, Arvind Sudarsanam
Utah State University, USA
"High Level - Application Analysis Techniques &
Architectures - to Explore Design possibilities for
Reduced Reconfiguration Area Overheads in FPGAs
executing Compute Intensive Applications"

Jing Lu, John Lockwood
Washington University in St. Louis, USA
"IPSec Implementation on Xilinx Virtex-II Pro FPGA
and Its Application"

16.20 16.40 Short Break

16.40 17.40 Session 13 Memory Architectures

Session Chair: TBD
Ron Sass, University of Kansas, USA
Pradeep Nalabalapu, Ambarella, Inc., USA
"Bandwidth Management with a Reconfigurable Data Cache"
Martin Schoeberl
"Design and Implementation of an Efficient Stack Machine"
Claudio Mucci, Antonio Deledda, Alberto Fazzi, Mirco Ferri,
Massimo Bocchi, ARCES - University of Bologna, Italy
Fabio Campi, Central R&D STMicroelectronics, Italy
"A Cycle-Accurate ISS for a Dynamically Reconfigurable
Processor Architecture"

17.40 18.00 Closing Remarks