/// EE 4755 - Digital Design Using HDLs // /// Material used in class 26 August 2016 module shift_right1 ( output logic [15:0] shifted, input wire [15:0] unshifted, input wire [3:0] amt ); localparam int width = 16; /// WARNING: To be correct only one of the four alternatives below /// should be present. // Implicit structural assign shifted = unshifted >> amt; // Explicit structural for MSB or o1(zn,amt[3],amt[2],amt[1],amt[0]); not n1(z,zn); and a1(shifted[15], unshifted[15], z); // Implicit structural easy way. always_comb shifted = unshifted >> amt; // Implicit structural hard way. always_comb begin for ( int i=0; i<width; i++ ) shifted[i] = i + amt >= width ? 0 : unshifted[ i + amt ]; end endmodule