/// LSU EE 4755 -- Fall 2016 -- Digital Design / HDL /// /// Verilog Review /// Contents // Review of Module Instantiation // Description of descriptive styles. /// References // :SV12: IEEE 1800-2012 -- The SystemVerilog Standard // http://standards.ieee.org/getieee/1800/download/1800-2012.pdf // This is for those already familiar with Verilog. // // :BV3: Brown & Vranesic, Fundamentals of Digital Logic with Verilog, 3rd Ed. // The text used in LSU EE 4720, 4730, and 4740. // This is for those who need to review basic Verilog. //////////////////////////////////////////////////////////////////////////////// /// Modules and Module Instantiation // :BV2:, :BV3: 2.10 -- Good description. // /// A module describes a part, // can be simpler than a gate // or more complex than an entire computer. // // A module is defined once (see example) and can be /instantiated/, // used by other modules, many times. Examples of instantiation // provided further below. // :Example: // // Definition of a module for the illustrated circuit. // //
// module pie ( output wire x, y, input wire a, b, c ); wire t1, t2; xor x1(t1,a,b); not n1(x,t1); and a1(t2,x,c); or o1(y,t2,b); endmodule // // The module above includes only primitives (the xor, not, and // or). In the next example a module will be defined in terms of other // modules. // :Example: // // Definition of a module which uses the module above. // module two_pie ( output wire o1, o2, input wire f, g, h, a ); wire i1, i2; pie apple(i1, i2, f, g, h ); pie cherry(o1, o2, i1, i2, a ); endmodule // // Illustration of the module above: //
//////////////////////////////////////////////////////////////////////////////// /// Descriptive Styles // :Def: Descriptive Style // // A set of rules for writing Verilog code. // :Def: Explicit Behavioral Form // // A descriptive style in which a module can not use continuous // assignment statements (assign) or procedural statements (code // within (initial and always). The module can instantiate primitives // and other modules. // // This style is easiest for synthesis programs to work with but // extremely tedious to write. // // The pie module above is in the explicit structural style. // :Def: Implicit Behavioral Form // // A descriptive style in which a module can not use procedural // statements (code within (initial and always). The module can // instantiate primitives and other modules, and can use continuous // assignments. // // This style is also easy for synthesis programs to work with // but can be tedious to write. // :Example: // // The module below is equivalent to the pie module, except that // it is in implicit structural form. module pie_implicit_structural ( output wire x, y, input wire a, b, c ); assign x = !( a ^ b ); assign y = x && c || b; endmodule // :Def: Synthesizable Behavioral Form // // A descriptive style in which a module can use procedural code, but // following rules for synthesizability. (Those rules are determined // by the synthesis program being used.) // :Example: // // The module below is equivalent to the pie module, except that // it is in synthesis behavioral form. module pie_behavioral ( output logic x, y, input wire a, b, c ); always_comb begin x = !( a ^ b ); y = x && c || b; end endmodule // :Example: // // Because of the $display system task, the module below is not in // synthesizable behavioral form, or any other descriptive style // defined above. // module pie_procedural ( output logic x, y, input wire a, b, c ); initial $display("Hello, from the pie_procedural module!\n"); always_comb begin x = !( a ^ b ); y = x && c || b; end endmodule